Botan
1.11.15
|
#include <cpuid.h>
Static Public Member Functions | |
static size_t | cache_line_size () |
static bool | has_adx () |
static bool | has_aes_ni () |
static bool | has_altivec () |
static bool | has_avx2 () |
static bool | has_avx512f () |
static bool | has_bmi2 () |
static bool | has_clmul () |
static bool | has_intel_sha () |
static bool | has_rdrand () |
static bool | has_rdseed () |
static bool | has_rdtsc () |
static bool | has_sse2 () |
static bool | has_sse41 () |
static bool | has_sse42 () |
static bool | has_ssse3 () |
static void | initialize () |
static void | print (std::ostream &o) |
static size_t Botan::CPUID::cache_line_size | ( | ) | [inline, static] |
Return a best guess of the cache line size
Definition at line 30 of file cpuid.h.
Referenced by Botan::prefetch_readonly(), and Botan::prefetch_readwrite().
{ initialize(); return g_cache_line_size; }
static bool Botan::CPUID::has_adx | ( | ) | [inline, static] |
static bool Botan::CPUID::has_aes_ni | ( | ) | [inline, static] |
static bool Botan::CPUID::has_altivec | ( | ) | [inline, static] |
Check if the processor supports AltiVec/VMX
Definition at line 35 of file cpuid.h.
{ initialize(); return g_altivec_capable; }
static bool Botan::CPUID::has_avx2 | ( | ) | [inline, static] |
static bool Botan::CPUID::has_avx512f | ( | ) | [inline, static] |
static bool Botan::CPUID::has_bmi2 | ( | ) | [inline, static] |
static bool Botan::CPUID::has_clmul | ( | ) | [inline, static] |
static bool Botan::CPUID::has_intel_sha | ( | ) | [inline, static] |
static bool Botan::CPUID::has_rdrand | ( | ) | [inline, static] |
Check if the processor supports RDRAND
Definition at line 112 of file cpuid.h.
Referenced by Botan::Intel_Rdrand::poll().
{ return x86_processor_flags_has(CPUID_RDRAND_BIT); }
static bool Botan::CPUID::has_rdseed | ( | ) | [inline, static] |
static bool Botan::CPUID::has_rdtsc | ( | ) | [inline, static] |
Check if the processor supports RDTSC
Definition at line 40 of file cpuid.h.
Referenced by Botan::High_Resolution_Timestamp::poll().
{ return x86_processor_flags_has(CPUID_RDTSC_BIT); }
static bool Botan::CPUID::has_sse2 | ( | ) | [inline, static] |
static bool Botan::CPUID::has_sse41 | ( | ) | [inline, static] |
static bool Botan::CPUID::has_sse42 | ( | ) | [inline, static] |
static bool Botan::CPUID::has_ssse3 | ( | ) | [inline, static] |
void Botan::CPUID::initialize | ( | ) | [static] |
Probe the CPU and see what extensions are supported
Definition at line 185 of file cpuid.cpp.
References Botan::clear_mem(), Botan::get_byte(), and Botan::same_mem().
{ if(g_initialized) return; #if defined(BOTAN_TARGET_CPU_IS_PPC_FAMILY) if(altivec_check_sysctl() || altivec_check_pvr_emul()) g_altivec_capable = true; #endif #if defined(BOTAN_TARGET_CPU_IS_X86_FAMILY) const u32bit INTEL_CPUID[3] = { 0x756E6547, 0x6C65746E, 0x49656E69 }; const u32bit AMD_CPUID[3] = { 0x68747541, 0x444D4163, 0x69746E65 }; u32bit cpuid[4] = { 0 }; X86_CPUID(0, cpuid); const u32bit max_supported_sublevel = cpuid[0]; if(max_supported_sublevel == 0) return; const bool is_intel = same_mem(cpuid + 1, INTEL_CPUID, 3); const bool is_amd = same_mem(cpuid + 1, AMD_CPUID, 3); X86_CPUID(1, cpuid); g_x86_processor_flags[0] = (static_cast<u64bit>(cpuid[2]) << 32) | cpuid[3]; if(is_intel) g_cache_line_size = 8 * get_byte(2, cpuid[1]); if(max_supported_sublevel >= 7) { clear_mem(cpuid, 4); X86_CPUID_SUBLEVEL(7, 0, cpuid); g_x86_processor_flags[1] = (static_cast<u64bit>(cpuid[2]) << 32) | cpuid[1]; } if(is_amd) { X86_CPUID(0x80000005, cpuid); g_cache_line_size = get_byte(3, cpuid[2]); } #endif #if defined(BOTAN_TARGET_ARCH_IS_X86_64) /* * If we don't have access to CPUID, we can still safely assume that * any x86-64 processor has SSE2 and RDTSC */ if(g_x86_processor_flags[0] == 0) g_x86_processor_flags[0] = (1 << CPUID_SSE2_BIT) | (1 << CPUID_RDTSC_BIT); #endif g_initialized = true; }
void Botan::CPUID::print | ( | std::ostream & | o | ) | [static] |
Definition at line 160 of file cpuid.cpp.
References CPUID_PRINT.
{ o << "CPUID flags: "; #define CPUID_PRINT(flag) do { if(has_##flag()) o << #flag << " "; } while(0) CPUID_PRINT(sse2); CPUID_PRINT(ssse3); CPUID_PRINT(sse41); CPUID_PRINT(sse42); CPUID_PRINT(avx2); CPUID_PRINT(avx512f); CPUID_PRINT(altivec); CPUID_PRINT(rdtsc); CPUID_PRINT(bmi2); CPUID_PRINT(clmul); CPUID_PRINT(aes_ni); CPUID_PRINT(rdrand); CPUID_PRINT(rdseed); CPUID_PRINT(intel_sha); CPUID_PRINT(adx); #undef CPUID_PRINT o << "\n"; }