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power.h
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00001 /* Copyright (c) 2006, 2007, 2008  Eric B. Weddington
00002    Copyright (c) 2011 Frédéric Nadeau
00003    All rights reserved.
00004 
00005    Redistribution and use in source and binary forms, with or without
00006    modification, are permitted provided that the following conditions are met:
00007 
00008    * Redistributions of source code must retain the above copyright
00009      notice, this list of conditions and the following disclaimer.
00010    * Redistributions in binary form must reproduce the above copyright
00011      notice, this list of conditions and the following disclaimer in
00012      the documentation and/or other materials provided with the
00013      distribution.
00014    * Neither the name of the copyright holders nor the names of
00015      contributors may be used to endorse or promote products derived
00016      from this software without specific prior written permission.
00017 
00018   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00019   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00020   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00021   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00022   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00023   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00024   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00025   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00026   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00027   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00028   POSSIBILITY OF SUCH DAMAGE. */
00029 
00030 /* $Id: power.h 2503 2016-02-07 22:59:47Z joerg_wunsch $ */
00031 
00032 #ifndef _AVR_POWER_H_
00033 #define _AVR_POWER_H_   1
00034 
00035 #include <avr/io.h>
00036 #include <stdint.h>
00037 
00038 
00039 /** \file */
00040 /** \defgroup avr_power <avr/power.h>: Power Reduction Management
00041 
00042 \code #include <avr/power.h>\endcode
00043 
00044 Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that 
00045 allow you to reduce power consumption by disabling or enabling various on-board 
00046 peripherals as needed. Some devices have the XTAL Divide Control Register
00047 (XDIV) which offer similar functionality as System Clock Prescale
00048 Register (CLKPR).
00049 
00050 There are many macros in this header file that provide an easy interface
00051 to enable or disable on-board peripherals to reduce power. See the table below.
00052 
00053 \note Not all AVR devices have a Power Reduction Register (for example
00054 the ATmega8). On those devices without a Power Reduction Register, the
00055 power reduction macros are not available..
00056 
00057 \note Not all AVR devices contain the same peripherals (for example, the LCD
00058 interface), or they will be named differently (for example, USART and 
00059 USART0). Please consult your device's datasheet, or the header file, to 
00060 find out which macros are applicable to your device.
00061 
00062 \note For device using the XTAL Divide Control Register (XDIV), when prescaler
00063 is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind
00064 that Timer/Counter0 source shall be less than ¼th of peripheral clock.
00065 Therefore, when using a typical 32.768 kHz crystal, one shall not scale
00066 the clock below 131.072 kHz.
00067 
00068 */
00069 
00070 
00071 /** \addtogroup avr_power
00072 
00073 \anchor avr_powermacros
00074 <small>
00075 <center>
00076 <table border="3">
00077   <tr>
00078     <td width="10%"><strong>Power Macro</strong></td>
00079     <td width="15%"><strong>Description</strong></td>
00080   </tr>
00081 
00082   <tr>
00083     <td>power_aca_disable()</td>
00084     <td>Disable the Analog Comparator on PortA.</td>
00085   </tr>
00086 
00087   <tr>
00088     <td>power_aca_enable()</td>
00089     <td>Enable the Analog Comparator on PortA.</td>
00090   </tr>
00091 
00092   <tr>
00093     <td>power_adc_enable()</td>
00094     <td>Enable the Analog to Digital Converter module.</td>
00095   </tr>
00096 
00097   <tr>
00098     <td>power_adc_disable()</td>
00099     <td>Disable the Analog to Digital Converter module.</td>
00100   </tr>
00101 
00102   <tr>
00103     <td>power_adca_disable()</td>
00104     <td>Disable the Analog to Digital Converter module on PortA</td>
00105   </tr>
00106 
00107   <tr>
00108     <td>power_adca_enable()</td>
00109     <td>Enable the Analog to Digital Converter module on PortA</td>
00110   </tr>
00111 
00112   <tr>
00113     <td>power_evsys_disable()</td>
00114     <td>Disable the EVSYS module</td>
00115   </tr>
00116 
00117   <tr>
00118     <td>power_evsys_enable()</td>
00119     <td>Enable the EVSYS module</td>
00120   </tr>
00121 
00122   <tr>
00123     <td>power_hiresc_disable()</td>
00124     <td>Disable the HIRES module on PortC</td>
00125   </tr>
00126 
00127   <tr>
00128     <td>power_hiresc_enable()</td>
00129     <td>Enable the HIRES module on PortC</td>
00130   </tr>
00131 
00132    <tr>
00133     <td>power_lcd_enable()</td>
00134     <td>Enable the LCD module.</td>
00135   </tr>
00136 
00137   <tr>
00138     <td>power_lcd_disable().</td>
00139     <td>Disable the LCD module.</td>
00140   </tr>
00141 
00142   <tr>
00143     <td>power_pga_enable()</td>
00144     <td>Enable the Programmable Gain Amplifier module.</td>
00145   </tr>
00146 
00147   <tr>
00148     <td>power_pga_disable()</td>
00149     <td>Disable the Programmable Gain Amplifier module.</td>
00150   </tr>
00151   
00152   <tr>
00153     <td>power_pscr_enable()</td>
00154     <td>Enable the Reduced Power Stage Controller module.</td>
00155   </tr>
00156 
00157   <tr>
00158     <td>power_pscr_disable()</td>
00159     <td>Disable the Reduced Power Stage Controller module.</td>
00160   </tr>
00161 
00162   <tr>
00163     <td>power_psc0_enable()</td>
00164     <td>Enable the Power Stage Controller 0 module.</td>
00165   </tr>
00166 
00167   <tr>
00168     <td>power_psc0_disable()</td>
00169     <td>Disable the Power Stage Controller 0 module.</td>
00170   </tr>
00171 
00172   <tr>
00173     <td>power_psc1_enable()</td>
00174     <td>Enable the Power Stage Controller 1 module.</td>
00175   </tr>
00176 
00177   <tr>
00178     <td>power_psc1_disable()</td>
00179     <td>Disable the Power Stage Controller 1 module.</td>
00180   </tr>
00181 
00182   <tr>
00183     <td>power_psc2_enable()</td>
00184     <td>Enable the Power Stage Controller 2 module.</td>
00185   </tr>
00186 
00187   <tr>
00188     <td>power_psc2_disable()</td>
00189     <td>Disable the Power Stage Controller 2 module.</td>
00190   </tr>
00191 
00192   <tr>
00193     <td>power_ram0_enable()</td>
00194     <td>Enable the SRAM block 0 .</td>
00195   </tr>
00196 
00197   <tr>
00198     <td>power_ram0_disable()</td>
00199     <td>Disable the SRAM block 0. </td>
00200   </tr>
00201 
00202   <tr>
00203     <td>power_ram1_enable()</td>
00204     <td>Enable the SRAM block 1 .</td>
00205   </tr>
00206 
00207   <tr>
00208     <td>power_ram1_disable()</td>
00209     <td>Disable the SRAM block 1. </td>
00210   </tr>
00211 
00212   <tr>
00213     <td>power_ram2_enable()</td>
00214     <td>Enable the SRAM block 2 .</td>
00215   </tr>
00216 
00217   <tr>
00218     <td>power_ram2_disable()</td>
00219     <td>Disable the SRAM block 2. </td>
00220   </tr>
00221 
00222   <tr>
00223     <td>power_ram3_enable()</td>
00224     <td>Enable the SRAM block 3 .</td>
00225   </tr>
00226 
00227   <tr>
00228     <td>power_ram3_disable()</td>
00229     <td>Disable the SRAM block 3. </td>
00230   </tr>
00231 
00232   <tr>
00233     <td>power_rtc_disable()</td>
00234     <td>Disable the RTC module</td>
00235   </tr>
00236 
00237   <tr>
00238     <td>power_rtc_enable()</td>
00239     <td>Enable the RTC module</td>
00240   </tr>
00241 
00242   <tr>
00243     <td>power_spi_enable()</td>
00244     <td>Enable the Serial Peripheral Interface module.</td>
00245   </tr>
00246 
00247   <tr>
00248     <td>power_spi_disable()</td>
00249     <td>Disable the Serial Peripheral Interface module.</td>
00250   </tr>
00251 
00252   <tr>
00253     <td>power_spic_disable()</td>
00254     <td>Disable the SPI module on PortC</td>
00255   </tr>
00256 
00257   <tr>
00258     <td>power_spic_enable()</td>
00259     <td>Enable the SPI module on PortC</td>
00260   </tr>
00261 
00262   <tr>
00263     <td>power_spid_disable()</td>
00264     <td>Disable the SPI module on PortD</td>
00265   </tr>
00266 
00267   <tr>
00268     <td>power_spid_enable()</td>
00269     <td>Enable the SPI module on PortD</td>
00270   </tr>
00271 
00272   <tr>
00273     <td>power_tc0c_disable()</td>
00274     <td>Disable the TC0 module on PortC</td>
00275   </tr>
00276 
00277   <tr>
00278     <td>power_tc0c_enable()</td>
00279     <td>Enable the TC0 module on PortC</td>
00280   </tr>
00281 
00282   <tr>
00283     <td>power_tc0d_disable()</td>
00284     <td>Disable the TC0 module on PortD</td>
00285   </tr>
00286 
00287   <tr>
00288     <td>power_tc0d_enable()</td>
00289     <td>Enable the TC0 module on PortD</td>
00290   </tr>
00291 
00292   <tr>
00293     <td>power_tc0e_disable()</td>
00294     <td>Disable the TC0 module on PortE</td>
00295   </tr>
00296 
00297   <tr>
00298     <td>power_tc0e_enable()</td>
00299     <td>Enable the TC0 module on PortE</td>
00300   </tr>
00301 
00302   <tr>
00303     <td>power_tc0f_disable()</td>
00304     <td>Disable the TC0 module on PortF</td>
00305   </tr>
00306 
00307   <tr>
00308     <td>power_tc0f_enable()</td>
00309     <td>Enable the TC0 module on PortF</td>
00310   </tr>
00311 
00312   <tr>
00313     <td>power_tc1c_disable()</td>
00314     <td>Disable the TC1 module on PortC</td>
00315   </tr>
00316 
00317   <tr>
00318     <td>power_tc1c_enable()</td>
00319     <td>Enable the TC1 module on PortC</td>
00320   </tr>
00321 
00322   <tr>
00323     <td>power_twic_disable()</td>
00324     <td>Disable the Two Wire Interface module on PortC</td>
00325   </tr>
00326 
00327   <tr>
00328     <td>power_twic_enable()</td>
00329     <td>Enable the Two Wire Interface module on PortC</td>
00330   </tr>
00331 
00332   <tr>
00333     <td>power_twie_disable()</td>
00334     <td>Disable the Two Wire Interface module on PortE</td>
00335   </tr>
00336 
00337   <tr>
00338     <td>power_twie_enable()</td>
00339     <td>Enable the Two Wire Interface module on PortE</td>
00340   </tr>
00341 
00342   <tr>
00343     <td>power_timer0_enable()</td>
00344     <td>Enable the Timer 0 module.</td>
00345   </tr>
00346 
00347   <tr>
00348     <td>power_timer0_disable()</td>
00349     <td>Disable the Timer 0 module.</td>
00350   </tr>
00351 
00352   <tr>
00353     <td>power_timer1_enable()</td>
00354     <td>Enable the Timer 1 module.</td>
00355   </tr>
00356 
00357   <tr>
00358     <td>power_timer1_disable()</td>
00359     <td>Disable the Timer 1 module.</td>
00360   </tr>
00361 
00362   <tr>
00363     <td>power_timer2_enable()</td>
00364     <td>Enable the Timer 2 module.</td>
00365   </tr>
00366 
00367   <tr>
00368     <td>power_timer2_disable()</td>
00369     <td>Disable the Timer 2 module.</td>
00370   </tr>
00371 
00372   <tr>
00373     <td>power_timer3_enable()</td>
00374     <td>Enable the Timer 3 module.</td>
00375   </tr>
00376 
00377   <tr>
00378     <td>power_timer3_disable()</td>
00379     <td>Disable the Timer 3 module.</td>
00380   </tr>
00381 
00382   <tr>
00383     <td>power_timer4_enable()</td>
00384     <td>Enable the Timer 4 module.</td>
00385   </tr>
00386 
00387   <tr>
00388     <td>power_timer4_disable()</td>
00389     <td>Disable the Timer 4 module.</td>
00390   </tr>
00391 
00392   <tr>
00393     <td>power_timer5_enable()</td>
00394     <td>Enable the Timer 5 module.</td>
00395   </tr>
00396 
00397   <tr>
00398     <td>power_timer5_disable()</td>
00399     <td>Disable the Timer 5 module.</td>
00400   </tr>
00401 
00402   <tr>
00403     <td>power_twi_enable()</td>
00404     <td>Enable the Two Wire Interface module.</td>
00405   </tr>
00406 
00407   <tr>
00408     <td>power_twi_disable()</td>
00409     <td>Disable the Two Wire Interface module.</td>
00410   </tr>
00411 
00412   <tr>
00413     <td>power_usart_enable()</td>
00414     <td>Enable the USART module.</td>
00415   </tr>
00416 
00417   <tr>
00418     <td>power_usart_disable()</td>
00419     <td>Disable the USART module.</td>
00420   </tr>
00421 
00422   <tr>
00423     <td>power_usart0_enable()</td>
00424     <td>Enable the USART 0 module.</td>
00425   </tr>
00426 
00427   <tr>
00428     <td>power_usart0_disable()</td>
00429     <td>Disable the USART 0 module.</td>
00430   </tr>
00431 
00432   <tr>
00433     <td>power_usart1_enable()</td>
00434     <td>Enable the USART 1 module.</td>
00435   </tr>
00436 
00437   <tr>
00438     <td>power_usart1_disable()</td>
00439     <td>Disable the USART 1 module.</td>
00440   </tr>
00441 
00442   <tr>
00443     <td>power_usart2_enable()</td>
00444     <td>Enable the USART 2 module.</td>
00445   </tr>
00446 
00447   <tr>
00448     <td>power_usart2_disable()</td>
00449     <td>Disable the USART 2 module.</td>
00450   </tr>
00451 
00452   <tr>
00453     <td>power_usart3_enable()</td>
00454     <td>Enable the USART 3 module.</td>
00455   </tr>
00456 
00457   <tr>
00458     <td>power_usart3_disable()</td>
00459     <td>Disable the USART 3 module.</td>
00460   </tr>
00461 
00462   <tr>
00463     <td>power_usartc0_disable()</td>
00464     <td> Disable the USART0 module on PortC</td>
00465   </tr>
00466 
00467   <tr>
00468     <td>power_usartc0_enable()</td>
00469     <td> Enable the USART0 module on PortC</td>
00470   </tr>
00471 
00472   <tr>
00473     <td>power_usartd0_disable()</td>
00474     <td> Disable the USART0 module on PortD</td>
00475   </tr>
00476 
00477   <tr>
00478     <td>power_usartd0_enable()</td>
00479     <td> Enable the USART0 module on PortD</td>
00480   </tr>
00481 
00482   <tr>
00483     <td>power_usarte0_disable()</td>
00484     <td> Disable the USART0 module on PortE</td>
00485   </tr>
00486 
00487   <tr>
00488     <td>power_usarte0_enable()</td>
00489     <td> Enable the USART0 module on PortE</td>
00490   </tr>
00491 
00492   <tr>
00493     <td>power_usartf0_disable()</td>
00494     <td> Disable the USART0 module on PortF</td>
00495   </tr>
00496 
00497   <tr>
00498     <td>power_usartf0_enable()</td>
00499     <td> Enable the USART0 module on PortF</td>
00500   </tr>
00501 
00502   <tr>
00503     <td>power_usb_enable()</td>
00504     <td>Enable the USB module.</td>
00505   </tr>
00506 
00507   <tr>
00508     <td>power_usb_disable()</td>
00509     <td>Disable the USB module.</td>
00510   </tr>
00511 
00512   <tr>
00513     <td>power_usi_enable()</td>
00514     <td>Enable the Universal Serial Interface module.</td>
00515   </tr>
00516 
00517   <tr>
00518     <td>power_usi_disable()</td>
00519     <td>Disable the Universal Serial Interface module.</td>
00520   </tr>
00521 
00522   <tr>
00523     <td>power_vadc_enable()</td>
00524     <td>Enable the Voltage ADC module.</td>
00525   </tr>
00526 
00527   <tr>
00528     <td>power_vadc_disable()</td>
00529     <td>Disable the Voltage ADC module.</td>
00530   </tr>
00531 
00532   <tr>
00533     <td>power_all_enable()</td>
00534     <td>Enable all modules.</td>
00535   </tr>
00536 
00537   <tr>
00538     <td>power_all_disable()</td>
00539     <td>Disable all modules.</td>
00540   </tr>
00541 </table>
00542 </center>
00543 </small>
00544 
00545 @} */
00546 
00547 #if defined(__AVR_HAVE_PRR_PRADC)
00548 #define power_adc_enable()      (PRR &= (uint8_t)~(1 << PRADC))
00549 #define power_adc_disable()     (PRR |= (uint8_t)(1 << PRADC))
00550 #endif
00551 
00552 #if defined(__AVR_HAVE_PRR_PRCAN)
00553 #define power_can_enable()      (PRR &= (uint8_t)~(1 << PRCAN))
00554 #define power_can_disable()     (PRR |= (uint8_t)(1 << PRCAN))
00555 #endif
00556 
00557 #if defined(__AVR_HAVE_PRR_PRLCD)
00558 #define power_lcd_enable()      (PRR &= (uint8_t)~(1 << PRLCD))
00559 #define power_lcd_disable()     (PRR |= (uint8_t)(1 << PRLCD))
00560 #endif
00561 
00562 #if defined(__AVR_HAVE_PRR_PRLIN)
00563 #define power_lin_enable()      (PRR &= (uint8_t)~(1 << PRLIN))
00564 #define power_lin_disable()     (PRR |= (uint8_t)(1 << PRLIN))
00565 #endif
00566 
00567 #if defined(__AVR_HAVE_PRR_PRPSC)
00568 #define power_psc_enable()      (PRR &= (uint8_t)~(1 << PRPSC))
00569 #define power_psc_disable()     (PRR |= (uint8_t)(1 << PRPSC))
00570 #endif
00571 
00572 #if defined(__AVR_HAVE_PRR_PRPSC0)
00573 #define power_psc0_enable()     (PRR &= (uint8_t)~(1 << PRPSC0))
00574 #define power_psc0_disable()    (PRR |= (uint8_t)(1 << PRPSC0))
00575 #endif
00576 
00577 #if defined(__AVR_HAVE_PRR_PRPSC1)
00578 #define power_psc1_enable()     (PRR &= (uint8_t)~(1 << PRPSC1))
00579 #define power_psc1_disable()    (PRR |= (uint8_t)(1 << PRPSC1))
00580 #endif
00581 
00582 #if defined(__AVR_HAVE_PRR_PRPSC2)
00583 #define power_psc2_enable()     (PRR &= (uint8_t)~(1 << PRPSC2))
00584 #define power_psc2_disable()    (PRR |= (uint8_t)(1 << PRPSC2))
00585 #endif
00586 
00587 #if defined(__AVR_HAVE_PRR_PRSCR)
00588 #define power_pscr_enable()     (PRR &= (uint8_t)~(1 << PRPSCR))
00589 #define power_pscr_disable()    (PRR |= (uint8_t)(1 << PRPSCR))
00590 #endif
00591 
00592 #if defined(__AVR_HAVE_PRR_PRSPI)
00593 #define power_spi_enable()      (PRR &= (uint8_t)~(1 << PRSPI))
00594 #define power_spi_disable()     (PRR |= (uint8_t)(1 << PRSPI))
00595 #endif
00596 
00597 #if defined(__AVR_HAVE_PRR_PRTIM0)
00598 #define power_timer0_enable()   (PRR &= (uint8_t)~(1 << PRTIM0))
00599 #define power_timer0_disable()  (PRR |= (uint8_t)(1 << PRTIM0))
00600 #endif
00601 
00602 #if defined(__AVR_HAVE_PRR_PRTIM1)
00603 #define power_timer1_enable()   (PRR &= (uint8_t)~(1 << PRTIM1))
00604 #define power_timer1_disable()  (PRR |= (uint8_t)(1 << PRTIM1))
00605 #endif
00606 
00607 #if defined(__AVR_HAVE_PRR_PRTIM2)
00608 #define power_timer2_enable()   (PRR &= (uint8_t)~(1 << PRTIM2))
00609 #define power_timer2_disable()  (PRR |= (uint8_t)(1 << PRTIM2))
00610 #endif
00611 
00612 #if defined(__AVR_HAVE_PRR_PRTWI)
00613 #define power_twi_enable()      (PRR &= (uint8_t)~(1 << PRTWI))
00614 #define power_twi_disable()     (PRR |= (uint8_t)(1 << PRTWI))
00615 #endif
00616 
00617 #if defined(__AVR_HAVE_PRR_PRUSART)
00618 #define power_usart_enable()    (PRR &= (uint8_t)~(1 << PRUSART))
00619 #define power_usart_disable()   (PRR |= (uint8_t)(1 << PRUSART))
00620 #endif
00621 
00622 #if defined(__AVR_HAVE_PRR_PRUSART0)
00623 #define power_usart0_enable()   (PRR &= (uint8_t)~(1 << PRUSART0))
00624 #define power_usart0_disable()  (PRR |= (uint8_t)(1 << PRUSART0))
00625 #endif
00626 
00627 #if defined(__AVR_HAVE_PRR_PRUSART1)
00628 #define power_usart1_enable()   (PRR &= (uint8_t)~(1 << PRUSART1))
00629 #define power_usart1_disable()  (PRR |= (uint8_t)(1 << PRUSART1))
00630 #endif
00631 
00632 #if defined(__AVR_HAVE_PRR_PRUSI)
00633 #define power_usi_enable()      (PRR &= (uint8_t)~(1 << PRUSI))
00634 #define power_usi_disable()     (PRR |= (uint8_t)(1 << PRUSI))
00635 #endif
00636 
00637 #if defined(__AVR_HAVE_PRR0_PRADC)
00638 #define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
00639 #define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
00640 #endif
00641 
00642 #if defined(__AVR_HAVE_PRR0_PRC0)
00643 #define power_clock_output_enable()     (PRR0 &= (uint8_t)~(1 << PRCO))
00644 #define power_clock_output_disable()    (PRR0 |= (uint8_t)(1 << PRCO))
00645 #endif
00646 
00647 #if defined(__AVR_HAVE_PRR0_PRCRC)
00648 #define power_crc_enable()              (PRR0 &= (uint8_t)~(1 << PRCRC))
00649 #define power_crc_disable()             (PRR0 |= (uint8_t)(1 << PRCRC))
00650 #endif
00651 
00652 #if defined(__AVR_HAVE_PRR0_PRCU)
00653 #define power_crypto_enable()           (PRR0 &= (uint8_t)~(1 << PRCU))
00654 #define power_crypto_disable()          (PRR0 |= (uint8_t)(1 << PRCU))
00655 #endif
00656 
00657 #if defined(__AVR_HAVE_PRR0_PRDS)
00658 #define power_irdriver_enable()         (PRR0 &= (uint8_t)~(1 << PRDS))
00659 #define power_irdriver_disable()        (PRR0 |= (uint8_t)(1 << PRDS))
00660 #endif
00661 
00662 #if defined(__AVR_HAVE_PRR0_PRLFR)
00663 #define power_lfreceiver_enable()       (PRR0 &= (uint8_t)~(1 << PRLFR))            
00664 #define power_lfreceiver_disable()      (PRR0 |= (uint8_t)(1 << PRLFR))            
00665 #endif
00666 
00667 #if defined(__AVR_HAVE_PRR0_PRLIN)
00668 #define power_lin_enable()              (PRR0 &= (uint8_t)~(1 << PRLIN))
00669 #define power_lin_disable()             (PRR0 |= (uint8_t)(1 << PRLIN))
00670 #endif
00671 
00672 #if defined(__AVR_HAVE_PRR0_PRPGA)
00673 #define power_pga_enable()              (PRR0 &= (uint8_t)~(1 << PRPGA))
00674 #define power_pga_disable()             (PRR0 |= (uint8_t)(1 << PRPGA))
00675 #endif
00676 
00677 #if defined(__AVR_HAVE_PRR0_PRRXDC)
00678 #define power_receive_dsp_control_enable()  (PRR0 &= (uint8_t)~(1 << PRRXDC))
00679 #define power_receive_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRRXDC))
00680 #endif
00681 
00682 #if defined(__AVR_HAVE_PRR0_PRSPI)
00683 #define power_spi_enable()              (PRR0 &= (uint8_t)~(1 << PRSPI))
00684 #define power_spi_disable()             (PRR0 |= (uint8_t)(1 << PRSPI))
00685 #endif
00686 
00687 #if defined(__AVR_HAVE_PRR0_PRT0)
00688 #define power_timer0_enable()           (PRR0 &= (uint8_t)~(1 << PRT0))
00689 #define power_timer0_disable()          (PRR0 |= (uint8_t)(1 << PRT0))
00690 #endif
00691 
00692 #if defined(__AVR_HAVE_PRR0_PRTIM0)
00693 #define power_timer0_enable()           (PRR0 &= (uint8_t)~(1 << PRTIM0))
00694 #define power_timer0_disable()          (PRR0 |= (uint8_t)(1 << PRTIM0))
00695 #endif
00696 
00697 #if defined(__AVR_HAVE_PRR0_PRT1)
00698 #define power_timer1_enable()           (PRR0 &= (uint8_t)~(1 << PRT1))
00699 #define power_timer1_disable()          (PRR0 |= (uint8_t)(1 << PRT1))
00700 #endif
00701 
00702 #if defined(__AVR_HAVE_PRR0_PRTIM1)
00703 #define power_timer1_enable()           (PRR0 &= (uint8_t)~(1 << PRTIM1))
00704 #define power_timer1_disable()          (PRR0 |= (uint8_t)(1 << PRTIM1))
00705 #endif
00706 
00707 #if defined(__AVR_HAVE_PRR0_PRT2)
00708 #define power_timer2_enable()           (PRR0 &= (uint8_t)~(1 << PRT2))
00709 #define power_timer2_disable()          (PRR0 |= (uint8_t)(1 << PRT2))
00710 #endif
00711 
00712 #if defined(__AVR_HAVE_PRR0_PRTIM2)
00713 #define power_timer2_enable()           (PRR0 &= (uint8_t)~(1 << PRTIM2))
00714 #define power_timer2_disable()          (PRR0 |= (uint8_t)(1 << PRTIM2))
00715 #endif
00716 
00717 #if defined(__AVR_HAVE_PRR0_PRT3)
00718 #define power_timer3_enable()           (PRR0 &= (uint8_t)~(1 << PRT3))
00719 #define power_timer3_disable()          (PRR0 |= (uint8_t)(1 << PRT3))
00720 #endif
00721 
00722 #if defined(__AVR_HAVE_PRR0_PRTM)
00723 #define power_timermodulator_enable()   (PRR0 &= (uint8_t)~(1 << PRTM))
00724 #define power_timermodulator_disable()  (PRR0 |= (uint8_t)(1 << PRTM))
00725 #endif
00726 
00727 #if defined(__AVR_HAVE_PRR0_PRTWI)
00728 #define power_twi_enable()              (PRR0 &= (uint8_t)~(1 << PRTWI))
00729 #define power_twi_disable()             (PRR0 |= (uint8_t)(1 << PRTWI))
00730 #endif
00731 
00732 #if defined(__AVR_HAVE_PRR0_PRTXDC)
00733 #define power_transmit_dsp_control_enable()   (PRR0 &= (uint8_t)~(1 << PRTXDC))
00734 #define power_transmit_dsp_control_disable()  (PRR0 |= (uint8_t)(1 << PRTXDC))
00735 #endif
00736 
00737 #if defined(__AVR_HAVE_PRR0_PRUSART0)
00738 #define power_usart0_enable()           (PRR0 &= (uint8_t)~(1 << PRUSART0))
00739 #define power_usart0_disable()          (PRR0 |= (uint8_t)(1 << PRUSART0))
00740 #endif
00741 
00742 #if defined(__AVR_HAVE_PRR0_PRUSART1)
00743 #define power_usart1_enable()           (PRR0 &= (uint8_t)~(1 << PRUSART1))
00744 #define power_usart1_disable()          (PRR0 |= (uint8_t)(1 << PRUSART1))
00745 #endif
00746 
00747 #if defined(__AVR_HAVE_PRR0_PRVADC)
00748 #define power_vadc_enable()             (PRR0 &= (uint8_t)~(1 << PRVADC))
00749 #define power_vadc_disable()            (PRR0 |= (uint8_t)(1 << PRVADC))
00750 #endif
00751 
00752 #if defined(__AVR_HAVE_PRR0_PRVM)
00753 #define power_voltage_monitor_enable()  (PRR0 &= (uint8_t)~(1 << PRVM))
00754 #define power_voltage_monitor_disable() (PRR0 |= (uint8_t)(1 << PRVM))
00755 #endif
00756 
00757 #if defined(__AVR_HAVE_PRR0_PRVRM)
00758 #define power_vrm_enable()              (PRR0 &= (uint8_t)~(1 << PRVRM))
00759 #define power_vrm_disable()             (PRR0 |= (uint8_t)(1 << PRVRM))
00760 #endif
00761 
00762 #if defined(__AVR_HAVE_PRR1_PRAES)
00763 #define power_aes_enable()              (PRR1 &= (uint8_t)~(1 << PRAES))
00764 #define power_aes_disable()             (PRR1 |= (uint8_t)(1 << PRAES))
00765 #endif
00766 
00767 #if defined(__AVR_HAVE_PRR1_PRCI)
00768 #define power_cinterface_enable()       (PRR1 &= (uint8_t)~(1 << PRCI))
00769 #define power_cinterface_disable()      (PRR1 |= (uint8_t)(1 << PRCI))
00770 #endif
00771 
00772 #if defined(__AVR_HAVE_PRR1_PRHSSPI)
00773 #define power_hsspi_enable()            (PRR1 &= (uint8_t)~(1 << PRHSSPI))
00774 #define power_hsspi_disable()           (PRR1 |= (uint8_t)(1 << PRHSSPI))
00775 #endif
00776 
00777 #if defined(__AVR_HAVE_PRR1_PRKB)
00778 #define power_kb_enable()               (PRR1 &= (uint8_t)~(1 << PRKB))
00779 #define power_kb_disable()              (PRR1 |= (uint8_t)(1 << PRKB))
00780 #endif
00781 
00782 #if defined(__AVR_HAVE_PRR1_PRLFR)
00783 #define power_lfreceiver_enable()       (PRR1 &= (uint8_t)~(1 << PRLFR))            
00784 #define power_lfreceiver_disable()      (PRR1 |= (uint8_t)(1 << PRLFR))            
00785 #endif
00786 
00787 #if defined(__AVR_HAVE_PRR1_PRSCI)
00788 #define power_sci_enable()              (PRR1 &= (uint8_t)~(1 << PRSCI))
00789 #define power_sci_disable()             (PRR1 |= (uint8_t)(1 << PRSCI))
00790 #endif
00791 
00792 #if defined(__AVR_HAVE_PRR1_PRT1)
00793 #define power_timer1_enable()           (PRR1 &= (uint8_t)~(1 << PRT1))
00794 #define power_timer1_disable()          (PRR1 |= (uint8_t)(1 << PRT1))
00795 #endif
00796 
00797 #if defined(__AVR_HAVE_PRR1_PRT2)
00798 #define power_timer2_enable()           (PRR1 &= (uint8_t)~(1 << PRT2))
00799 #define power_timer2_disable()          (PRR1 |= (uint8_t)(1 << PRT2))
00800 #endif
00801 
00802 #if defined(__AVR_HAVE_PRR1_PRT3)
00803 #define power_timer3_enable()           (PRR1 &= (uint8_t)~(1 << PRT3))
00804 #define power_timer3_disable()          (PRR1 |= (uint8_t)(1 << PRT3))
00805 #endif
00806 
00807 #if defined(__AVR_HAVE_PRR1_PRT4)
00808 #define power_timer4_enable()           (PRR1 &= (uint8_t)~(1 << PRT4))
00809 #define power_timer4_disable()          (PRR1 |= (uint8_t)(1 << PRT4))
00810 #endif
00811 
00812 #if defined(__AVR_HAVE_PRR1_PRT5)
00813 #define power_timer5_enable()           (PRR1 &= (uint8_t)~(1 << PRT5))
00814 #define power_timer5_disable()          (PRR1 |= (uint8_t)(1 << PRT5))
00815 #endif
00816 
00817 #if defined(__AVR_HAVE_PRR1_PRTIM3)
00818 #define power_timer3_enable()           (PRR1 &= (uint8_t)~(1 << PRTIM3))
00819 #define power_timer3_disable()          (PRR1 |= (uint8_t)(1 << PRTIM3))
00820 #endif
00821 
00822 #if defined(__AVR_HAVE_PRR1_PRTIM4)
00823 #define power_timer4_enable()           (PRR1 &= (uint8_t)~(1 << PRTIM4))
00824 #define power_timer4_disable()          (PRR1 |= (uint8_t)(1 << PRTIM4))
00825 #endif
00826 
00827 #if defined(__AVR_HAVE_PRR1_PRTIM5)
00828 #define power_timer5_enable()           (PRR1 &= (uint8_t)~(1 << PRTIM5))
00829 #define power_timer5_disable()          (PRR1 |= (uint8_t)(1 << PRTIM5))
00830 #endif
00831 
00832 #if defined(__AVR_HAVE_PRR1_PRTRX24)
00833 #define power_transceiver_enable()      (PRR1 &= (uint8_t)~(1 << PRTRX24))
00834 #define power_transceiver_disable()     (PRR1 |= (uint8_t)(1 << PRTRX24))
00835 #endif
00836 
00837 #if defined(__AVR_HAVE_PRR1_PRUSART1)
00838 #define power_usart1_enable()           (PRR1 &= (uint8_t)~(1 << PRUSART1))
00839 #define power_usart1_disable()          (PRR1 |= (uint8_t)(1 << PRUSART1))
00840 #endif
00841 
00842 #if defined(__AVR_HAVE_PRR1_PRUSART2)
00843 #define power_usart2_enable()           (PRR1 &= (uint8_t)~(1 << PRUSART2))
00844 #define power_usart2_disable()          (PRR1 |= (uint8_t)(1 << PRUSART2))
00845 #endif
00846 
00847 #if defined(__AVR_HAVE_PRR1_PRUSB)
00848 #define power_usb_enable()              (PRR1 &= (uint8_t)~(1 << PRUSB))
00849 #define power_usb_disable()             (PRR1 |= (uint8_t)(1 << PRUSB))
00850 #endif
00851 
00852 #if defined(__AVR_HAVE_PRR1_PRUSBH)
00853 #define power_usbh_enable()             (PRR1 &= (uint8_t)~(1 << PRUSBH))
00854 #define power_usbh_disable()            (PRR1 |= (uint8_t)(1 << PRUSBH))
00855 #endif
00856 
00857 #if defined(__AVR_HAVE_PRR2_PRDF)
00858 #define power_data_fifo_enable()        (PRR2 &= (uint8_t)~(1 << PRDF))
00859 #define power_data_fifo_disable()       (PRR2 |= (uint8_t)(1 << PRDF))
00860 #endif
00861 
00862 #if defined(__AVR_HAVE_PRR2_PRIDS)
00863 #define power_id_scan_enable()          (PRR2 &= (uint8_t)~(1 << PRIDS))
00864 #define power_id_scan_disable()         (PRR2 |= (uint8_t)(1 << PRIDS))
00865 #endif
00866 
00867 #if defined(__AVR_HAVE_PRR2_PRRAM0)
00868 #define power_ram0_enable()             (PRR2 &= (uint8_t)~(1 << PRRAM0))
00869 #define power_ram0_disable()            (PRR2 |= (uint8_t)(1 << PRRAM0))
00870 #endif
00871 
00872 #if defined(__AVR_HAVE_PRR2_PRRAM1)
00873 #define power_ram1_enable()             (PRR2 &= (uint8_t)~(1 << PRRAM1))
00874 #define power_ram1_disable()            (PRR2 |= (uint8_t)(1 << PRRAM1))
00875 #endif
00876 
00877 #if defined(__AVR_HAVE_PRR2_PRRAM2)
00878 #define power_ram2_enable()             (PRR2 &= (uint8_t)~(1 << PRRAM2))
00879 #define power_ram2_disable()            (PRR2 |= (uint8_t)(1 << PRRAM2))
00880 #endif
00881 
00882 #if defined(__AVR_HAVE_PRR2_PRRAM3)
00883 #define power_ram3_enable()             (PRR2 &= (uint8_t)~(1 << PRRAM3))
00884 #define power_ram3_disable()            (PRR2 |= (uint8_t)(1 << PRRAM3))
00885 #endif
00886 
00887 #if defined(__AVR_HAVE_PRR2_PRRS)
00888 #define power_rssi_buffer_enable()      (PRR2 &= (uint8_t)~(1 << PRRS))
00889 #define power_rssi_buffer_disable()     (PRR2 |= (uint8_t)(1 << PRRS))
00890 #endif
00891 
00892 #if defined(__AVR_HAVE_PRR2_PRSF)
00893 #define power_preamble_rssi_fifo_enable()       (PRR2 &= (uint8_t)~(1 << PRSF))
00894 #define power_preamble_rssi_fifo_disable()      (PRR2 |= (uint8_t)(1 << PRSF))
00895 #endif
00896 
00897 #if defined(__AVR_HAVE_PRR2_PRSSM)
00898 #define power_sequencer_state_machine_enable()  (PRR2 &= (uint8_t)~(1 << PRSSM))
00899 #define power_sequencer_state_machine_disable() (PRR2 |= (uint8_t)(1 << PRSSM))
00900 #endif
00901 
00902 #if defined(__AVR_HAVE_PRR2_PRTM)
00903 #define power_tx_modulator_enable()     (PRR2 &= (uint8_t)~(1 << PRTM))
00904 #define power_tx_modulator_disable()    (PRR2 |= (uint8_t)(1 << PRTM))
00905 #endif
00906 
00907 #if defined(__AVR_HAVE_PRR2_PRXA)
00908 #define power_rx_buffer_A_enable()      (PRR2 &= (uint8_t)~(1 << PRXA))
00909 #define power_rx_buffer_A_disable()     (PRR2 |= (uint8_t)(1 << PRXA))
00910 #endif
00911 
00912 #if defined(__AVR_HAVE_PRR2_PRXB)
00913 #define power_rx_buffer_B_enable()      (PRR2 &= (uint8_t)~(1 << PRXB))
00914 #define power_rx_buffer_B_disable()     (PRR2 |= (uint8_t)(1 << PRXB))
00915 #endif
00916 
00917 #if defined(__AVR_HAVE_PRGEN_AES)
00918 #define power_aes_enable()              (PR_PRGEN &= (uint8_t)~(PR_AES_bm))
00919 #define power_aes_disable()             (PR_PRGEN |= (uint8_t)PR_AES_bm)
00920 #endif
00921 
00922 #if defined(__AVR_HAVE_PRGEN_DMA)
00923 #define power_dma_enable()              (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
00924 #define power_dma_disable()             (PR_PRGEN |= (uint8_t)PR_DMA_bm)
00925 #endif
00926 
00927 #if defined(__AVR_HAVE_PRGEN_EBI)
00928 #define power_ebi_enable()              (PR_PRGEN &= (uint8_t)~(PR_EBI_bm))
00929 #define power_ebi_disable()             (PR_PRGEN |= (uint8_t)PR_EBI_bm)
00930 #endif
00931 
00932 #if defined(__AVR_HAVE_PRGEN_EDMA)
00933 #define power_edma_enable()             (PR_PRGEN &= (uint8_t)~(PR_EDMA_bm))
00934 #define power_edma_disable()            (PR_PRGEN |= (uint8_t)PR_EDMA_bm)
00935 #endif
00936 
00937 #if defined(__AVR_HAVE_PRGEN_EVSYS)
00938 #define power_evsys_enable()            (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
00939 #define power_evsys_disable()           (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
00940 #endif
00941 
00942 #if defined(__AVR_HAVE_PRGEN_LCD)
00943 #define power_lcd_enable()              (PR_PRGEN &= (uint8_t)~(PR_LCD_bm))
00944 #define power_lcd_disable()             (PR_PRGEN |= (uint8_t)PR_LCD_bm)
00945 #endif
00946 
00947 #if defined(__AVR_HAVE_PRGEN_RTC)
00948 #define power_rtc_enable()              (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
00949 #define power_rtc_disable()             (PR_PRGEN |= (uint8_t)PR_RTC_bm)
00950 #endif
00951 
00952 #if defined(__AVR_HAVE_PRGEN_USB)
00953 #define power_usb_enable()              (PR_PRGEN &= (uint8_t)~(PR_USB_bm))
00954 #define power_usb_disable()             (PR_PRGEN &= (uint8_t)(PR_USB_bm))
00955 #endif
00956 
00957 #if defined(__AVR_HAVE_PRGEN_XCL)
00958 #define power_xcl_enable()              (PR_PRGEN &= (uint8_t)~(PR_XCL_bm))
00959 #define power_xcl_disable()             (PR_PRGEN |= (uint8_t)PR_XCL_bm)
00960 #endif
00961 
00962 #if defined(__AVR_HAVE_PRPA_AC)
00963 #define power_aca_enable()      (PR_PRPA &= (uint8_t)~(PR_AC_bm))
00964 #define power_aca_disable()     (PR_PRPA |= (uint8_t)PR_AC_bm)
00965 #endif
00966 
00967 #if defined(__AVR_HAVE_PRPA_ADC)
00968 #define power_adca_enable()     (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
00969 #define power_adca_disable()    (PR_PRPA |= (uint8_t)PR_ADC_bm)
00970 #endif
00971 
00972 #if defined(__AVR_HAVE_PRPA_DAC)
00973 #define power_daca_enable()     (PR_PRPA &= (uint8_t)~(PR_DAC_bm))
00974 #define power_daca_disable()    (PR_PRPA |= (uint8_t)PR_DAC_bm)
00975 #endif
00976 
00977 #if defined(__AVR_HAVE_PRPB_AC)
00978 #define power_acb_enable()      (PR_PRPB &= (uint8_t)~(PR_AC_bm))
00979 #define power_acb_disable()     (PR_PRPB |= (uint8_t)PR_AC_bm)
00980 #endif
00981 
00982 #if defined(__AVR_HAVE_PRPB_ADC)
00983 #define power_adcb_enable()     (PR_PRPB &= (uint8_t)~(PR_ADC_bm))
00984 #define power_adcb_disable()    (PR_PRPB |= (uint8_t)PR_ADC_bm)
00985 #endif
00986 
00987 #if defined(__AVR_HAVE_PRPB_DAC)
00988 #define power_dacb_enable()     (PR_PRPB &= (uint8_t)~(PR_DAC_bm))
00989 #define power_dacb_disable()    (PR_PRPB |= (uint8_t)PR_DAC_bm)
00990 #endif
00991 
00992 #if defined(__AVR_HAVE_PRPC_HIRES)
00993 #define power_hiresc_enable()   (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
00994 #define power_hiresc_disable()  (PR_PRPC |= (uint8_t)PR_HIRES_bm)
00995 #endif
00996 
00997 #if defined(__AVR_HAVE_PRPC_SPI)
00998 #define power_spic_enable()     (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
00999 #define power_spic_disable()    (PR_PRPC |= (uint8_t)PR_SPI_bm)
01000 #endif
01001 
01002 #if defined(__AVR_HAVE_PRPC_TC0)
01003 #define power_tc0c_enable()     (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
01004 #define power_tc0c_disable()    (PR_PRPC |= (uint8_t)PR_TC0_bm)
01005 #endif
01006 
01007 #if defined(__AVR_HAVE_PRPC_TC1)
01008 #define power_tc1c_enable()     (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
01009 #define power_tc1c_disable()    (PR_PRPC |= (uint8_t)PR_TC1_bm)
01010 #endif
01011 
01012 #if defined(__AVR_HAVE_PRPC_TC4)
01013 #define power_tc4c_enable()     (PR_PRPC  &= (uint8_t)~(PR_TC4_bm))
01014 #define power_tc4c_disable()    (PR_PRPC  |= (uint8_t)PR_TC4_bm)
01015 #endif
01016 
01017 #if defined(__AVR_HAVE_PRPC_TC5)
01018 #define power_tc5c_enable()     (PR_PRPC  &= (uint8_t)~(PR_TC5_bm))
01019 #define power_tc5c_disable()    (PR_PRPC  |= (uint8_t)PR_TC5_bm)
01020 #endif
01021 
01022 #if defined(__AVR_HAVE_PRPC_TWI)
01023 #define power_twic_enable()     (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
01024 #define power_twic_disable()    (PR_PRPC |= (uint8_t)PR_TWI_bm)
01025 #endif
01026 
01027 #if defined(__AVR_HAVE_PRPC_USART0)
01028 #define power_usartc0_enable()  (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
01029 #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
01030 #endif
01031 
01032 #if defined(__AVR_HAVE_PRPC_USART1)
01033 #define power_usartc1_enable()  (PR_PRPC &= (uint8_t)~(PR_USART1_bm))
01034 #define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm)
01035 #endif
01036 
01037 #if defined(__AVR_HAVE_PRPD_HIRES)
01038 #define power_hiresd_enable()   (PR_PRPD &= (uint8_t)~(PR_HIRES_bm))
01039 #define power_hiresd_disable()  (PR_PRPD |= (uint8_t)PR_HIRES_bm)
01040 #endif
01041 
01042 #if defined(__AVR_HAVE_PRPD_SPI)
01043 #define power_spid_enable()     (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
01044 #define power_spid_disable()    (PR_PRPD |= (uint8_t)PR_SPI_bm)
01045 #endif
01046 
01047 #if defined(__AVR_HAVE_PRPD_TC0)
01048 #define power_tc0d_enable()     (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
01049 #define power_tc0d_disable()    (PR_PRPD |= (uint8_t)PR_TC0_bm)
01050 #endif
01051 
01052 #if defined(__AVR_HAVE_PRPD_TC1)
01053 #define power_tc1d_enable()     (PR_PRPD &= (uint8_t)~(PR_TC1_bm))
01054 #define power_tc1d_disable()    (PR_PRPD |= (uint8_t)PR_TC1_bm)
01055 #endif
01056 
01057 #if defined(__AVR_HAVE_PRPD_TC5)
01058 #define power_tc5d_enable()     (PR_PRPD  &= (uint8_t)~(PR_TC5_bm))
01059 #define power_tc5d_disable()    (PR_PRPD  |= (uint8_t)PR_TC5_bm)
01060 #endif
01061 
01062 #if defined(__AVR_HAVE_PRPD_TWI)
01063 #define power_twid_enable()     (PR_PRPD &= (uint8_t)~(PR_TWI_bm))
01064 #define power_twid_disable()    (PR_PRPD |= (uint8_t)PR_TWI_bm)
01065 #endif
01066 
01067 #if defined(__AVR_HAVE_PRPD_USART0)
01068 #define power_usartd0_enable()  (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
01069 #define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
01070 #endif
01071 
01072 #if defined(__AVR_HAVE_PRPD_USART1)
01073 #define power_usartd1_enable()  (PR_PRPD &= (uint8_t)~(PR_USART1_bm))
01074 #define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm)
01075 #endif
01076 
01077 #if defined(__AVR_HAVE_PRPE_HIRES)
01078 #define power_hirese_enable()   (PR_PRPE &= (uint8_t)~(PR_HIRES_bm))
01079 #define power_hirese_disable()  (PR_PRPE |= (uint8_t)PR_HIRES_bm)
01080 #endif
01081 
01082 #if defined(__AVR_HAVE_PRPE_SPI)
01083 #define power_spie_enable()     (PR_PRPE &= (uint8_t)~(PR_SPI_bm))
01084 #define power_spie_disable()    (PR_PRPE |= (uint8_t)PR_SPI_bm)
01085 #endif
01086 
01087 #if defined(__AVR_HAVE_PRPE_TC0)
01088 #define power_tc0e_enable()     (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
01089 #define power_tc0e_disable()    (PR_PRPE |= (uint8_t)PR_TC0_bm)
01090 #endif
01091 
01092 #if defined(__AVR_HAVE_PRPE_TC1)
01093 #define power_tc1e_enable()     (PR_PRPE &= (uint8_t)~(PR_TC1_bm))
01094 #define power_tc1e_disable()    (PR_PRPE |= (uint8_t)PR_TC1_bm)
01095 #endif
01096 
01097 #if defined(__AVR_HAVE_PRPE_TWI)
01098 #define power_twie_enable()     (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
01099 #define power_twie_disable()    (PR_PRPE |= (uint8_t)PR_TWI_bm)
01100 #endif
01101 
01102 #if defined(__AVR_HAVE_PRPE_USART0)
01103 #define power_usarte0_enable()  (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
01104 #define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
01105 #endif
01106 
01107 #if defined(__AVR_HAVE_PRPE_USART1)
01108 #define power_usarte1_enable()  (PR_PRPE &= (uint8_t)~(PR_USART1_bm))
01109 #define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm)
01110 #endif
01111 
01112 #if defined(__AVR_HAVE_PRPF_HIRES)
01113 #define power_hiresf_enable()   (PR_PRPF &= (uint8_t)~(PR_HIRES_bm))
01114 #define power_hiresf_disable()  (PR_PRPF |= (uint8_t)PR_HIRES_bm)
01115 #endif
01116 
01117 #if defined(__AVR_HAVE_PRPF_SPI)
01118 #define power_spif_enable()     (PR_PRPF &= (uint8_t)~(PR_SPI_bm))
01119 #define power_spif_disable()    (PR_PRPF |= (uint8_t)PR_SPI_bm)
01120 #endif
01121 
01122 #if defined(__AVR_HAVE_PRPF_TC0)
01123 #define power_tc0f_enable()     (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
01124 #define power_tc0f_disable()    (PR_PRPF |= (uint8_t)PR_TC0_bm)
01125 #endif
01126 
01127 #if defined(__AVR_HAVE_PRPF_TC1)
01128 #define power_tc1f_enable()     (PR_PRPF &= (uint8_t)~(PR_TC1_bm))
01129 #define power_tc1f_disable()    (PR_PRPF |= (uint8_t)PR_TC1_bm)
01130 #endif
01131 
01132 #if defined(__AVR_HAVE_PRPF_TWI)
01133 #define power_twif_enable()     (PR_PRPF &= (uint8_t)~(PR_TWI_bm))
01134 #define power_twif_disable()    (PR_PRPF |= (uint8_t)PR_TWI_bm)
01135 #endif
01136 
01137 #if defined(__AVR_HAVE_PRPF_USART0)
01138 #define power_usartf0_enable()  (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
01139 #define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
01140 #endif
01141 
01142 #if defined(__AVR_HAVE_PRPF_USART1)
01143 #define power_usartf1_enable()  (PR_PRPF &= (uint8_t)~(PR_USART1_bm))
01144 #define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm)
01145 #endif
01146 
01147 static __inline void
01148 __attribute__ ((__always_inline__))
01149 __power_all_enable()
01150 {
01151 #ifdef __AVR_HAVE_PRR
01152     PRR &= (uint8_t)~(__AVR_HAVE_PRR);
01153 #endif
01154 
01155 #ifdef __AVR_HAVE_PRR0
01156     PRR0 &= (uint8_t)~(__AVR_HAVE_PRR0);
01157 #endif
01158 
01159 #ifdef __AVR_HAVE_PRR1
01160     PRR1 &= (uint8_t)~(__AVR_HAVE_PRR1);
01161 #endif
01162 
01163 #ifdef __AVR_HAVE_PRR2
01164    PRR2 &= (uint8_t)~(__AVR_HAVE_PRR2);
01165 #endif
01166 
01167 #ifdef __AVR_HAVE_PRGEN
01168     PR_PRGEN &= (uint8_t)~(__AVR_HAVE_PRGEN);
01169 #endif
01170 
01171 #ifdef __AVR_HAVE_PRPA
01172     PR_PRPA &= (uint8_t)~(__AVR_HAVE_PRPA);
01173 #endif
01174 
01175 #ifdef __AVR_HAVE_PRPB
01176     PR_PRPB &= (uint8_t)~(__AVR_HAVE_PRPB);
01177 #endif
01178 
01179 #ifdef __AVR_HAVE_PRPC
01180     PR_PRPC &= (uint8_t)~(__AVR_HAVE_PRPC);
01181 #endif
01182 
01183 #ifdef __AVR_HAVE_PRPD
01184     PR_PRPD &= (uint8_t)~(__AVR_HAVE_PRPD);
01185 #endif
01186 
01187 #ifdef __AVR_HAVE_PRPE
01188     PR_PRPE &= (uint8_t)~(__AVR_HAVE_PRPE);
01189 #endif
01190 
01191 #ifdef __AVR_HAVE_PRPF
01192     PR_PRPF &= (uint8_t)~(__AVR_HAVE_PRPF);
01193 #endif
01194 }
01195 
01196 static __inline void
01197 __attribute__ ((__always_inline__))
01198 __power_all_disable()
01199 {
01200 #ifdef __AVR_HAVE_PRR
01201     PRR |= (uint8_t)(__AVR_HAVE_PRR);
01202 #endif
01203 
01204 #ifdef __AVR_HAVE_PRR0
01205     PRR0 |= (uint8_t)(__AVR_HAVE_PRR0);
01206 #endif
01207 
01208 #ifdef __AVR_HAVE_PRR1
01209     PRR1 |= (uint8_t)(__AVR_HAVE_PRR1);
01210 #endif
01211 
01212 #ifdef __AVR_HAVE_PRR2
01213     PRR2 |= (uint8_t)(__AVR_HAVE_PRR2);
01214 #endif
01215 
01216 #ifdef __AVR_HAVE_PRGEN
01217     PR_PRGEN |= (uint8_t)(__AVR_HAVE_PRGEN);
01218 #endif
01219 
01220 #ifdef __AVR_HAVE_PRPA
01221     PR_PRPA |= (uint8_t)(__AVR_HAVE_PRPA);
01222 #endif
01223 
01224 #ifdef __AVR_HAVE_PRPB
01225     PR_PRPB |= (uint8_t)(__AVR_HAVE_PRPB);
01226 #endif
01227 
01228 #ifdef __AVR_HAVE_PRPC
01229     PR_PRPC |= (uint8_t)(__AVR_HAVE_PRPC);
01230 #endif
01231 
01232 #ifdef __AVR_HAVE_PRPD
01233     PR_PRPD |= (uint8_t)(__AVR_HAVE_PRPD);
01234 #endif
01235 
01236 #ifdef __AVR_HAVE_PRPE
01237     PR_PRPE |= (uint8_t)(__AVR_HAVE_PRPE);
01238 #endif
01239 
01240 #ifdef __AVR_HAVE_PRPF
01241     PR_PRPF |= (uint8_t)(__AVR_HAVE_PRPF);
01242 #endif
01243 }
01244 
01245 #ifndef __DOXYGEN__
01246 #ifndef power_all_enable
01247 #define power_all_enable() __power_all_enable()
01248 #endif
01249 
01250 #ifndef power_all_disable
01251 #define power_all_disable() __power_all_disable()
01252 #endif
01253 #endif  /* !__DOXYGEN__ */
01254 
01255 
01256 #if defined(__AVR_AT90CAN32__) \
01257 || defined(__AVR_AT90CAN64__) \
01258 || defined(__AVR_AT90CAN128__) \
01259 || defined(__AVR_AT90PWM1__) \
01260 || defined(__AVR_AT90PWM2__) \
01261 || defined(__AVR_AT90PWM2B__) \
01262 || defined(__AVR_AT90PWM3__) \
01263 || defined(__AVR_AT90PWM3B__) \
01264 || defined(__AVR_AT90PWM81__) \
01265 || defined(__AVR_AT90PWM161__) \
01266 || defined(__AVR_AT90PWM216__) \
01267 || defined(__AVR_AT90PWM316__) \
01268 || defined(__AVR_AT90SCR100__) \
01269 || defined(__AVR_AT90USB646__) \
01270 || defined(__AVR_AT90USB647__) \
01271 || defined(__AVR_AT90USB82__) \
01272 || defined(__AVR_AT90USB1286__) \
01273 || defined(__AVR_AT90USB1287__) \
01274 || defined(__AVR_AT90USB162__) \
01275 || defined(__AVR_ATA5505__) \
01276 || defined(__AVR_ATA5272__) \
01277 || defined(__AVR_ATmega1280__) \
01278 || defined(__AVR_ATmega1281__) \
01279 || defined(__AVR_ATmega1284__) \
01280 || defined(__AVR_ATmega128RFA1__) \
01281 || defined(__AVR_ATmega1284RFR2__) \
01282 || defined(__AVR_ATmega128RFR2__) \
01283 || defined(__AVR_ATmega1284P__) \
01284 || defined(__AVR_ATmega162__) \
01285 || defined(__AVR_ATmega164A__) \
01286 || defined(__AVR_ATmega164P__) \
01287 || defined(__AVR_ATmega164PA__) \
01288 || defined(__AVR_ATmega165__) \
01289 || defined(__AVR_ATmega165A__) \
01290 || defined(__AVR_ATmega165P__) \
01291 || defined(__AVR_ATmega165PA__) \
01292 || defined(__AVR_ATmega168__) \
01293 || defined(__AVR_ATmega168P__) \
01294 || defined(__AVR_ATmega168PA__) \
01295 || defined(__AVR_ATmega169__) \
01296 || defined(__AVR_ATmega169A__) \
01297 || defined(__AVR_ATmega169P__) \
01298 || defined(__AVR_ATmega169PA__) \
01299 || defined(__AVR_ATmega16U4__) \
01300 || defined(__AVR_ATmega2560__) \
01301 || defined(__AVR_ATmega2561__) \
01302 || defined(__AVR_ATmega2564RFR2__) \
01303 || defined(__AVR_ATmega256RFR2__) \
01304 || defined(__AVR_ATmega324A__) \
01305 || defined(__AVR_ATmega324P__) \
01306 || defined(__AVR_ATmega325__) \
01307 || defined(__AVR_ATmega325A__) \
01308 || defined(__AVR_ATmega325PA__) \
01309 || defined(__AVR_ATmega3250__) \
01310 || defined(__AVR_ATmega3250A__) \
01311 || defined(__AVR_ATmega3250PA__) \
01312 || defined(__AVR_ATmega328__) \
01313 || defined(__AVR_ATmega328P__) \
01314 || defined(__AVR_ATmega329__) \
01315 || defined(__AVR_ATmega329A__) \
01316 || defined(__AVR_ATmega329P__) \
01317 || defined(__AVR_ATmega329PA__) \
01318 || defined(__AVR_ATmega3290__) \
01319 || defined(__AVR_ATmega3290A__) \
01320 || defined(__AVR_ATmega3290PA__) \
01321 || defined(__AVR_ATmega32C1__) \
01322 || defined(__AVR_ATmega32M1__) \
01323 || defined(__AVR_ATmega32U2__) \
01324 || defined(__AVR_ATmega32U4__) \
01325 || defined(__AVR_ATmega32U6__) \
01326 || defined(__AVR_ATmega48__) \
01327 || defined(__AVR_ATmega48A__) \
01328 || defined(__AVR_ATmega48PA__) \
01329 || defined(__AVR_ATmega48P__) \
01330 || defined(__AVR_ATmega640__) \
01331 || defined(__AVR_ATmega649P__) \
01332 || defined(__AVR_ATmega644__) \
01333 || defined(__AVR_ATmega644A__) \
01334 || defined(__AVR_ATmega644P__) \
01335 || defined(__AVR_ATmega644PA__) \
01336 || defined(__AVR_ATmega645__) \
01337 || defined(__AVR_ATmega645A__) \
01338 || defined(__AVR_ATmega645P__) \
01339 || defined(__AVR_ATmega6450__) \
01340 || defined(__AVR_ATmega6450A__) \
01341 || defined(__AVR_ATmega6450P__) \
01342 || defined(__AVR_ATmega649__) \
01343 || defined(__AVR_ATmega649A__) \
01344 || defined(__AVR_ATmega6490__) \
01345 || defined(__AVR_ATmega6490A__) \
01346 || defined(__AVR_ATmega6490P__) \
01347 || defined(__AVR_ATmega644RFR2__) \
01348 || defined(__AVR_ATmega64RFR2__) \
01349 || defined(__AVR_ATmega88__) \
01350 || defined(__AVR_ATmega88P__) \
01351 || defined(__AVR_ATmega8U2__) \
01352 || defined(__AVR_ATmega16U2__) \
01353 || defined(__AVR_ATmega32U2__) \
01354 || defined(__AVR_ATtiny48__) \
01355 || defined(__AVR_ATtiny167__) \
01356 || defined(__DOXYGEN__)
01357 
01358 
01359 /** \addtogroup avr_power
01360 
01361 Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that
01362 allows you to decrease the system clock frequency and the power consumption
01363 when the need for processing power is low.
01364 On some earlier AVRs (ATmega103, ATmega64, ATmega128), similar
01365 functionality can be achieved through the XTAL Divide Control Register.
01366 Below are two macros and an enumerated type that can be used to
01367 interface to the Clock Prescale Register or
01368 XTAL Divide Control Register.
01369 
01370 \note Not all AVR devices have a clock prescaler. On those devices
01371 without a Clock Prescale Register or XTAL Divide Control Register, these
01372 macros are not available.
01373 */
01374 
01375 
01376 /** \addtogroup avr_power
01377 \code 
01378 typedef enum
01379 {
01380     clock_div_1 = 0,
01381     clock_div_2 = 1,
01382     clock_div_4 = 2,
01383     clock_div_8 = 3,
01384     clock_div_16 = 4,
01385     clock_div_32 = 5,
01386     clock_div_64 = 6,
01387     clock_div_128 = 7,
01388     clock_div_256 = 8,
01389     clock_div_1_rc = 15, // ATmega128RFA1 only
01390 } clock_div_t;
01391 \endcode
01392 Clock prescaler setting enumerations for device using
01393 System Clock Prescale Register.
01394 
01395 \code
01396 typedef enum
01397 {
01398     clock_div_1 = 1,
01399     clock_div_2 = 2,
01400     clock_div_4 = 4,
01401     clock_div_8 = 8,
01402     clock_div_16 = 16,
01403     clock_div_32 = 32,
01404     clock_div_64 = 64,
01405     clock_div_128 = 128
01406 } clock_div_t;
01407 \endcode
01408 Clock prescaler setting enumerations for device using
01409 XTAL Divide Control Register.
01410 
01411 */
01412 #ifndef __DOXYGEN__
01413 typedef enum
01414 {
01415     clock_div_1 = 0,
01416     clock_div_2 = 1,
01417     clock_div_4 = 2,
01418     clock_div_8 = 3,
01419     clock_div_16 = 4,
01420     clock_div_32 = 5,
01421     clock_div_64 = 6,
01422     clock_div_128 = 7,
01423     clock_div_256 = 8
01424 #if defined(__AVR_ATmega128RFA1__) \
01425 || defined(__AVR_ATmega2564RFR2__) \
01426 || defined(__AVR_ATmega1284RFR2__) \
01427 || defined(__AVR_ATmega644RFR2__) \
01428 || defined(__AVR_ATmega256RFR2__) \
01429 || defined(__AVR_ATmega128RFR2__) \
01430 || defined(__AVR_ATmega64RFR2__)
01431     , clock_div_1_rc = 15
01432 #endif
01433 } clock_div_t;
01434 
01435 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
01436 #endif  /* !__DOXYGEN__ */
01437 
01438 /**
01439    \ingroup avr_power
01440    \fn clock_prescale_set(clock_div_t x)
01441 
01442 Set the clock prescaler register select bits, selecting a system clock
01443 division setting. This function is inlined, even if compiler
01444 optimizations are disabled.
01445 
01446 The type of \c x is \c clock_div_t.
01447 
01448 \note For device with XTAL Divide Control Register (XDIV), \c x can actually range
01449 from 1 to 129. Thus, one does not need to use \c clock_div_t type as argument.
01450 */
01451 void clock_prescale_set(clock_div_t __x)
01452 {
01453     uint8_t __tmp = _BV(CLKPCE);
01454     __asm__ __volatile__ (
01455         "in __tmp_reg__,__SREG__" "\n\t"
01456         "cli" "\n\t"
01457         "sts %1, %0" "\n\t"
01458         "sts %1, %2" "\n\t"
01459         "out __SREG__, __tmp_reg__"
01460         : /* no outputs */
01461         : "d" (__tmp),
01462           "M" (_SFR_MEM_ADDR(CLKPR)),
01463           "d" (__x)
01464         : "r0");
01465 }
01466 
01467 /** \addtogroup avr_power
01468 \def clock_prescale_get()
01469 Gets and returns the clock prescaler register setting. The return type is \c clock_div_t.
01470 
01471 \note For device with XTAL Divide Control Register (XDIV), return can actually
01472 range from 1 to 129. Care should be taken has the return value could differ from the
01473 typedef enum clock_div_t. This should only happen if clock_prescale_set was previously
01474 called with a value other than those defined by \c clock_div_t.
01475 */
01476 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
01477 
01478 #elif defined(__AVR_ATmega16HVB__) \
01479 || defined(__AVR_ATmega16HVBREVB__) \
01480 || defined(__AVR_ATmega32HVB__) \
01481 || defined(__AVR_ATmega32HVBREVB__)
01482 
01483 typedef enum
01484 {
01485     clock_div_1 = 0,
01486     clock_div_2 = 1,
01487     clock_div_4 = 2,
01488     clock_div_8 = 3
01489 } clock_div_t;
01490 
01491 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
01492 
01493 void clock_prescale_set(clock_div_t __x)
01494 {
01495     uint8_t __tmp = _BV(CLKPCE);
01496     __asm__ __volatile__ (
01497         "in __tmp_reg__,__SREG__" "\n\t"
01498         "cli" "\n\t"
01499         "sts %1, %0" "\n\t"
01500         "sts %1, %2" "\n\t"
01501         "out __SREG__, __tmp_reg__"
01502         : /* no outputs */
01503         : "d" (__tmp),
01504           "M" (_SFR_MEM_ADDR(CLKPR)),
01505           "d" (__x)
01506         : "r0");
01507 }
01508 
01509 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)))
01510 
01511 #elif defined(__AVR_ATA5790__) \
01512 || defined (__AVR_ATA5795__)
01513 
01514 typedef enum
01515 {
01516     clock_div_1 = 0,
01517     clock_div_2 = 1,
01518     clock_div_4 = 2,
01519     clock_div_8 = 3,
01520     clock_div_16 = 4,
01521     clock_div_32 = 5,
01522     clock_div_64 = 6,
01523     clock_div_128 = 7,
01524 } clock_div_t;
01525 
01526 static __inline__ void system_clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
01527 
01528 void system_clock_prescale_set(clock_div_t __x)
01529 {
01530     uint8_t __tmp = _BV(CLKPCE);
01531     __asm__ __volatile__ (
01532         "in __tmp_reg__,__SREG__" "\n\t"
01533         "cli" "\n\t"
01534         "out %1, %0" "\n\t"
01535         "out %1, %2" "\n\t"
01536         "out __SREG__, __tmp_reg__"
01537         : /* no outputs */
01538         : "d" (__tmp),
01539           "I" (_SFR_IO_ADDR(CLKPR)),
01540           "d" (__x)
01541         : "r0");
01542 }
01543 
01544 #define system_clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
01545 
01546 typedef enum
01547 {
01548     timer_clock_div_reset = 0,
01549     timer_clock_div_1 = 1,
01550     timer_clock_div_2 = 2,
01551     timer_clock_div_4 = 3,
01552     timer_clock_div_8 = 4,
01553     timer_clock_div_16 = 5,
01554     timer_clock_div_32 = 6,
01555     timer_clock_div_64 = 7
01556 } timer_clock_div_t;
01557 
01558 static __inline__ void timer_clock_prescale_set(timer_clock_div_t) __attribute__((__always_inline__));
01559 
01560 void timer_clock_prescale_set(timer_clock_div_t __x)
01561 {
01562     uint8_t __t;
01563     __asm__ __volatile__ (
01564         "in __tmp_reg__,__SREG__" "\n\t"
01565         "cli" "\n\t"
01566         "in %[temp],%[clkpr]" "\n\t"
01567         "out %[clkpr],%[enable]" "\n\t"
01568         "andi %[temp],%[not_CLTPS]" "\n\t"
01569         "or %[temp], %[set_value]" "\n\t"
01570         "out %[clkpr],%[temp]" "\n\t"
01571         "sei" "\n\t"
01572         "out __SREG__,__tmp_reg__" "\n\t"
01573         : /* no outputs */
01574         : [temp] "r" (__t),
01575           [clkpr] "I" (_SFR_IO_ADDR(CLKPR)),
01576           [enable] "r" (_BV(CLKPCE)),
01577           [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
01578           [set_value] "r" ((__x & 7) << 3)
01579         : "r0");
01580 }
01581 
01582 #define timer_clock_prescale_get()  (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
01583 
01584 #elif defined(__AVR_ATA6285__) \
01585 || defined(__AVR_ATA6286__)
01586 
01587 typedef enum
01588 {
01589     clock_div_1 = 0,
01590     clock_div_2 = 1,
01591     clock_div_4 = 2,
01592     clock_div_8 = 3,
01593     clock_div_16 = 4,
01594     clock_div_32 = 5,
01595     clock_div_64 = 6,
01596     clock_div_128 = 7
01597 } clock_div_t;
01598 
01599 static __inline__ void system_clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
01600 
01601 void system_clock_prescale_set(clock_div_t __x)
01602 {
01603     uint8_t __t;
01604     __asm__ __volatile__ (
01605         "in __tmp_reg__,__SREG__" "\n\t"
01606         "cli" "\n\t"
01607         "in %[temp],%[clpr]" "\n\t"
01608         "out %[clpr],%[enable]" "\n\t"
01609         "andi %[temp],%[not_CLKPS]" "\n\t"
01610         "or %[temp], %[set_value]" "\n\t"
01611         "out %[clpr],%[temp]" "\n\t"
01612         "sei" "\n\t"
01613         "out __SREG__,__tmp_reg__" "\n\t"
01614         : /* no outputs */
01615         : [temp] "r" (__t),
01616           [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
01617           [enable] "r" _BV(CLPCE),
01618           [not_CLKPS] "M" (0xFF & (~ ((1 << CLKPS2) | (1 << CLKPS1) | (1 << CLKPS0)))),
01619           [set_value] "r" (__x & 7)
01620         : "r0");
01621 }
01622 
01623 #define system_clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
01624 
01625 typedef enum
01626 {
01627     timer_clock_div_reset = 0,
01628     timer_clock_div_1 = 1,
01629     timer_clock_div_2 = 2,
01630     timer_clock_div_4 = 3,
01631     timer_clock_div_8 = 4,
01632     timer_clock_div_16 = 5,
01633     timer_clock_div_32 = 6,
01634     timer_clock_div_64 = 7
01635 } timer_clock_div_t;
01636 
01637 static __inline__ void timer_clock_prescale_set(timer_clock_div_t) __attribute__((__always_inline__));
01638 
01639 void timer_clock_prescale_set(timer_clock_div_t __x)
01640 {
01641     uint8_t __t;
01642     __asm__ __volatile__ (
01643         "in __tmp_reg__,__SREG__" "\n\t"
01644         "cli" "\n\t"
01645         "in %[temp],%[clpr]" "\n\t"
01646         "out %[clpr],%[enable]" "\n\t"
01647         "andi %[temp],%[not_CLTPS]" "\n\t"
01648         "or %[temp], %[set_value]" "\n\t"
01649         "out %[clpr],%[temp]" "\n\t"
01650         "sei" "\n\t"
01651         "out __SREG__,__tmp_reg__" "\n\t"
01652         : /* no outputs */
01653         : [temp] "r" (__t),
01654           [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
01655           [enable] "r" (_BV(CLPCE)),      
01656           [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
01657           [set_value] "r" ((__x & 7) << 3)
01658         : "r0");
01659 }
01660 
01661 #define timer_clock_prescale_get()  (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
01662 
01663 #elif defined(__AVR_ATtiny24__) \
01664 || defined(__AVR_ATtiny24A__) \
01665 || defined(__AVR_ATtiny44__) \
01666 || defined(__AVR_ATtiny44A__) \
01667 || defined(__AVR_ATtiny84__) \
01668 || defined(__AVR_ATtiny84A__) \
01669 || defined(__AVR_ATtiny25__) \
01670 || defined(__AVR_ATtiny45__) \
01671 || defined(__AVR_ATtiny85__) \
01672 || defined(__AVR_ATtiny261A__) \
01673 || defined(__AVR_ATtiny261__) \
01674 || defined(__AVR_ATtiny461__) \
01675 || defined(__AVR_ATtiny461A__) \
01676 || defined(__AVR_ATtiny861__) \
01677 || defined(__AVR_ATtiny861A__) \
01678 || defined(__AVR_ATtiny2313__) \
01679 || defined(__AVR_ATtiny2313A__) \
01680 || defined(__AVR_ATtiny4313__) \
01681 || defined(__AVR_ATtiny13__) \
01682 || defined(__AVR_ATtiny13A__) \
01683 || defined(__AVR_ATtiny43U__) \
01684 
01685 typedef enum
01686 {
01687     clock_div_1 = 0,
01688     clock_div_2 = 1,
01689     clock_div_4 = 2,
01690     clock_div_8 = 3,
01691     clock_div_16 = 4,
01692     clock_div_32 = 5,
01693     clock_div_64 = 6,
01694     clock_div_128 = 7,
01695     clock_div_256 = 8
01696 } clock_div_t;
01697 
01698 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
01699 
01700 void clock_prescale_set(clock_div_t __x)
01701 {
01702     uint8_t __tmp = _BV(CLKPCE);
01703     __asm__ __volatile__ (
01704         "in __tmp_reg__,__SREG__" "\n\t"
01705         "cli" "\n\t"
01706         "out %1, %0" "\n\t"
01707         "out %1, %2" "\n\t"
01708         "out __SREG__, __tmp_reg__"
01709         : /* no outputs */
01710         : "d" (__tmp),
01711           "I" (_SFR_IO_ADDR(CLKPR)),
01712           "d" (__x)
01713         : "r0");
01714 }
01715 
01716 
01717 #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
01718 
01719 #elif defined(__AVR_ATmega64__) \
01720 || defined(__AVR_ATmega103__) \
01721 || defined(__AVR_ATmega128__)
01722 
01723 //Enum is declared for code compatibility
01724 typedef enum
01725 {
01726     clock_div_1 = 1,
01727     clock_div_2 = 2,
01728     clock_div_4 = 4,
01729     clock_div_8 = 8,
01730     clock_div_16 = 16,
01731     clock_div_32 = 32,
01732     clock_div_64 = 64,
01733     clock_div_128 = 128
01734 } clock_div_t;
01735 
01736 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
01737 
01738 void clock_prescale_set(clock_div_t __x)
01739 {
01740     if((__x <= 0) || (__x > 129))
01741     {
01742         return;//Invalid value.
01743     }
01744     else
01745     {
01746         uint8_t __tmp = 0;
01747         //Algo explained:
01748         //1 - Clear XDIV in order for it to accept a new value (actually only
01749         //    XDIVEN need to be cleared, but clearing XDIV is faster than
01750         //    read-modify-write since we will rewrite XDIV later anyway)
01751         //2 - wait 8 clock cycle for stability, see datasheet erreta
01752         //3 - Exist if requested prescaller is 1
01753         //4 - Calculate XDIV6..0 value = 129 - __x
01754         //5 - Set XDIVEN bit in calculated value
01755         //6 - write XDIV with calculated value
01756         //7 - wait 8 clock cycle for stability, see datasheet erreta
01757         __asm__ __volatile__ (
01758             "in __tmp_reg__,__SREG__" "\n\t"
01759             "cli" "\n\t"
01760             "out %1, __zero_reg__" "\n\t"
01761             "nop" "\n\t"
01762             "nop" "\n\t"
01763             "nop" "\n\t"
01764             "nop" "\n\t"
01765             "nop" "\n\t"
01766             "nop" "\n\t"
01767             "nop" "\n\t"
01768             "nop" "\n\t"
01769             "cpi %0, 0x01" "\n\t"
01770             "breq L_%=" "\n\t"
01771             "ldi %2, 0x81" "\n\t" //129
01772             "sub %2, %0" "\n\t"
01773             "ori %2, 0x80" "\n\t" //128
01774             "out %1, %2" "\n\t"
01775             "nop" "\n\t"
01776             "nop" "\n\t"
01777             "nop" "\n\t"
01778             "nop" "\n\t"
01779             "nop" "\n\t"
01780             "nop" "\n\t"
01781             "nop" "\n\t"
01782             "nop" "\n\t"
01783             "L_%=: " "out __SREG__, __tmp_reg__"
01784             : /* no outputs */
01785             :"d" (__x),
01786              "I" (_SFR_IO_ADDR(XDIV)),
01787              "d" (__tmp)
01788             : "r0");
01789     }
01790 }
01791 
01792 static __inline__ clock_div_t clock_prescale_get(void) __attribute__((__always_inline__));
01793 
01794 clock_div_t clock_prescale_get(void)
01795 {
01796     if(bit_is_clear(XDIV, XDIVEN))
01797     {
01798         return 1;
01799     }
01800     else
01801     {
01802         return (clock_div_t)(129 - (XDIV & 0x7F));
01803     }
01804 }
01805  
01806 #elif defined(__AVR_ATtiny4__) \
01807 || defined(__AVR_ATtiny5__) \
01808 || defined(__AVR_ATtiny9__) \
01809 || defined(__AVR_ATtiny10__) \
01810 || defined(__AVR_ATtiny20__) \
01811 || defined(__AVR_ATtiny40__) \
01812 
01813 typedef enum 
01814 { 
01815     clock_div_1 = 0, 
01816     clock_div_2 = 1, 
01817     clock_div_4 = 2, 
01818     clock_div_8 = 3, 
01819     clock_div_16 = 4, 
01820     clock_div_32 = 5, 
01821     clock_div_64 = 6, 
01822     clock_div_128 = 7, 
01823     clock_div_256 = 8 
01824 } clock_div_t; 
01825 
01826 static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
01827 
01828 void clock_prescale_set(clock_div_t __x)
01829 {
01830     uint8_t __tmp = 0xD8;
01831     __asm__ __volatile__ (
01832         "in __tmp_reg__,__SREG__" "\n\t"
01833         "cli" "\n\t"
01834         "out %1, %0" "\n\t"
01835         "out %2, %3" "\n\t"
01836         "out __SREG__, __tmp_reg__"
01837         : /* no outputs */
01838         : "d" (__tmp),
01839           "I" (_SFR_IO_ADDR(CCP)),
01840           "I" (_SFR_IO_ADDR(CLKPSR)),
01841           "d" (__x)
01842         : "r16");
01843 }
01844 
01845 #define clock_prescale_get()  (clock_div_t)(CLKPSR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
01846  
01847 #endif
01848 
01849 #endif /* _AVR_POWER_H_ */
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