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wdt.h
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00001 /* Copyright (c) 2002, 2004 Marek Michalkiewicz
00002    Copyright (c) 2005, 2006, 2007 Eric B. Weddington
00003    All rights reserved.
00004 
00005    Redistribution and use in source and binary forms, with or without
00006    modification, are permitted provided that the following conditions are met:
00007 
00008    * Redistributions of source code must retain the above copyright
00009      notice, this list of conditions and the following disclaimer.
00010 
00011    * Redistributions in binary form must reproduce the above copyright
00012      notice, this list of conditions and the following disclaimer in
00013      the documentation and/or other materials provided with the
00014      distribution.
00015 
00016    * Neither the name of the copyright holders nor the names of
00017      contributors may be used to endorse or promote products derived
00018      from this software without specific prior written permission.
00019 
00020   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00021   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00022   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00023   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00024   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00025   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00026   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00027   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00028   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00029   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00030   POSSIBILITY OF SUCH DAMAGE. */
00031 
00032 /* $Id: wdt.h 2503 2016-02-07 22:59:47Z joerg_wunsch $ */
00033 
00034 /*
00035    avr/wdt.h - macros for AVR watchdog timer
00036  */
00037 
00038 #ifndef _AVR_WDT_H_
00039 #define _AVR_WDT_H_
00040 
00041 #include <avr/io.h>
00042 #include <stdint.h>
00043 
00044 /** \file */
00045 /** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
00046     \code #include <avr/wdt.h> \endcode
00047 
00048     This header file declares the interface to some inline macros
00049     handling the watchdog timer present in many AVR devices.  In order
00050     to prevent the watchdog timer configuration from being
00051     accidentally altered by a crashing application, a special timed
00052     sequence is required in order to change it.  The macros within
00053     this header file handle the required sequence automatically
00054     before changing any value.  Interrupts will be disabled during
00055     the manipulation.
00056 
00057     \note Depending on the fuse configuration of the particular
00058     device, further restrictions might apply, in particular it might
00059     be disallowed to turn off the watchdog timer.
00060 
00061     Note that for newer devices (ATmega88 and newer, effectively any
00062     AVR that has the option to also generate interrupts), the watchdog
00063     timer remains active even after a system reset (except a power-on
00064     condition), using the fastest prescaler value (approximately 15
00065     ms).  It is therefore required to turn off the watchdog early
00066     during program startup, the datasheet recommends a sequence like
00067     the following:
00068 
00069     \code
00070     #include <stdint.h>
00071     #include <avr/wdt.h>
00072 
00073     uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
00074 
00075     void get_mcusr(void) \
00076       __attribute__((naked)) \
00077       __attribute__((section(".init3")));
00078     void get_mcusr(void)
00079     {
00080       mcusr_mirror = MCUSR;
00081       MCUSR = 0;
00082       wdt_disable();
00083     }
00084     \endcode
00085 
00086     Saving the value of MCUSR in \c mcusr_mirror is only needed if the
00087     application later wants to examine the reset source, but in particular, 
00088     clearing the watchdog reset flag before disabling the
00089     watchdog is required, according to the datasheet.
00090 */
00091 
00092 /**
00093    \ingroup avr_watchdog
00094    Reset the watchdog timer.  When the watchdog timer is enabled,
00095    a call to this instruction is required before the timer expires,
00096    otherwise a watchdog-initiated device reset will occur. 
00097 */
00098 
00099 #define wdt_reset() __asm__ __volatile__ ("wdr")
00100 
00101 #ifndef __DOXYGEN__
00102 
00103 #if defined(WDP3)
00104 # define _WD_PS3_MASK       _BV(WDP3)
00105 #else
00106 # define _WD_PS3_MASK       0x00
00107 #endif
00108 
00109 #if defined(WDTCSR)
00110 #  define _WD_CONTROL_REG     WDTCSR
00111 #elif defined(WDTCR)
00112 #  define _WD_CONTROL_REG     WDTCR
00113 #else
00114 #  define _WD_CONTROL_REG     WDT
00115 #endif
00116 
00117 #if defined(WDTOE)
00118 #define _WD_CHANGE_BIT      WDTOE
00119 #else
00120 #define _WD_CHANGE_BIT      WDCE
00121 #endif
00122 
00123 #endif  /* !__DOXYGEN__ */
00124 
00125 
00126 /**
00127    \ingroup avr_watchdog
00128    Enable the watchdog timer, configuring it for expiry after
00129    \c timeout (which is a combination of the \c WDP0 through
00130    \c WDP2 bits to write into the \c WDTCR register; For those devices 
00131    that have a \c WDTCSR register, it uses the combination of the \c WDP0 
00132    through \c WDP3 bits).
00133 
00134    See also the symbolic constants \c WDTO_15MS et al.
00135 */
00136 
00137 
00138 #if defined(__AVR_XMEGA__)
00139 
00140 /*
00141    wdt_enable(timeout) for xmega devices
00142 ** write signature (CCP_IOREG_gc) that enables change of protected I/O
00143    registers to the CCP register
00144 ** At the same time,
00145    1) set WDT change enable (WDT_CEN_bm)
00146    2) enable WDT (WDT_ENABLE_bm)
00147    3) set timeout (timeout)
00148 ** Synchronization starts when ENABLE bit of WDT is set. So, wait till it
00149    finishes (SYNCBUSY of STATUS register is automatically cleared after the
00150    sync is finished).
00151 */
00152 #define wdt_enable(timeout) \
00153 do { \
00154 uint8_t temp; \
00155 __asm__ __volatile__ (         \
00156     "in __tmp_reg__, %[rampd]"              "\n\t" \
00157     "out %[rampd], __zero_reg__"            "\n\t" \
00158     "out %[ccp_reg], %[ioreg_cen_mask]"     "\n\t" \
00159     "sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \
00160     "1:lds %[tmp], %[wdt_status_reg]"       "\n\t" \
00161     "sbrc %[tmp], %[wdt_syncbusy_bit]"      "\n\t" \
00162     "rjmp 1b"                               "\n\t" \
00163     "out %[rampd], __tmp_reg__"             "\n\t" \
00164     : [tmp]                "=r" (temp) \
00165     : [rampd]              "I" (_SFR_IO_ADDR(RAMPD)),      \
00166       [ccp_reg]            "I" (_SFR_IO_ADDR(CCP)),        \
00167       [ioreg_cen_mask]     "r" ((uint8_t)CCP_IOREG_gc),     \
00168       [wdt_reg]            "n" (_SFR_MEM_ADDR(WDT_CTRL)),   \
00169       [wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \
00170       [wdt_status_reg]     "n" (_SFR_MEM_ADDR(WDT_STATUS)), \
00171       [wdt_syncbusy_bit]   "I" (WDT_SYNCBUSY_bm)            \
00172     : "r0" \
00173 ); \
00174 } while(0)
00175 
00176 #define wdt_disable() \
00177 __asm__ __volatile__ (  \
00178     "in __tmp_reg__, %[rampd]"          "\n\t" \
00179     "out %[rampd], __zero_reg__"        "\n\t" \
00180     "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
00181     "sts %[wdt_reg], %[disable_mask]"   "\n\t" \
00182     "out %[rampd], __tmp_reg__"         "\n\t" \
00183     : \
00184     : [rampd]             "I" (_SFR_IO_ADDR(RAMPD)),    \
00185       [ccp_reg]           "I" (_SFR_IO_ADDR(CCP)),      \
00186       [ioreg_cen_mask]    "r" ((uint8_t)CCP_IOREG_gc),   \
00187       [wdt_reg]           "n" (_SFR_MEM_ADDR(WDT_CTRL)), \
00188       [disable_mask]      "r" ((uint8_t)((~WDT_ENABLE_bm) | WDT_CEN_bm)) \
00189     : "r0" \
00190 );
00191 
00192 #elif defined(__AVR_TINY__)
00193 
00194 #define wdt_enable(value) \
00195 __asm__ __volatile__ ( \
00196     "in __tmp_reg__,__SREG__" "\n\t"  \
00197     "cli" "\n\t"  \
00198     "wdr" "\n\t"  \
00199     "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"  \
00200     "out %[WDTREG],%[WDVALUE]" "\n\t"  \
00201     "out __SREG__,__tmp_reg__" "\n\t"  \
00202     : /* no outputs */  \
00203     : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),  \
00204       [SIGNATURE] "r" ((uint8_t)0xD8), \
00205       [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
00206       [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
00207       | _BV(WDE) | (value & 0x07) )) \
00208     : "r16" \
00209 )
00210 
00211 #define wdt_disable() \
00212 do { \
00213 uint8_t temp_wd; \
00214 __asm__ __volatile__ ( \
00215     "in __tmp_reg__,__SREG__" "\n\t"  \
00216     "cli" "\n\t"  \
00217     "wdr" "\n\t"  \
00218     "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"  \
00219     "in  %[TEMP_WD],%[WDTREG]" "\n\t" \
00220     "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
00221     "out %[WDTREG],%[TEMP_WD]" "\n\t" \
00222     "out __SREG__,__tmp_reg__" "\n\t" \
00223     : /*no output */ \
00224     : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
00225       [SIGNATURE] "r" ((uint8_t)0xD8), \
00226       [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
00227       [TEMP_WD] "d" (temp_wd), \
00228       [WDVALUE] "n" (1 << WDE) \
00229     : "r16" \
00230 ); \
00231 }while(0)
00232 
00233 #elif defined(CCP)
00234 
00235 static __inline__
00236 __attribute__ ((__always_inline__))
00237 void wdt_enable (const uint8_t value)
00238 {
00239     if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG))
00240     {
00241         __asm__ __volatile__ (
00242             "in __tmp_reg__,__SREG__" "\n\t"
00243             "cli" "\n\t"
00244             "wdr" "\n\t"
00245             "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
00246             "sts %[WDTREG],%[WDVALUE]" "\n\t"
00247             "out __SREG__,__tmp_reg__" "\n\t"
00248             : /* no outputs */
00249             : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)),
00250             [SIGNATURE] "r" ((uint8_t)0xD8),
00251             [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
00252             [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
00253                 | _BV(WDE) | (value & 0x07) ))
00254             : "r0"
00255             );
00256     }
00257     else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P (_WD_CONTROL_REG))
00258     {
00259         __asm__ __volatile__ (
00260             "in __tmp_reg__,__SREG__" "\n\t"
00261             "cli" "\n\t"
00262             "wdr" "\n\t"
00263             "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
00264             "out %[WDTREG],%[WDVALUE]" "\n\t"
00265             "out __SREG__,__tmp_reg__" "\n\t"
00266             : /* no outputs */
00267             : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)),
00268             [SIGNATURE] "r" ((uint8_t)0xD8),
00269             [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
00270             [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
00271                 | _BV(WDE) | (value & 0x07) ))
00272             : "r0"
00273             );
00274     }
00275     else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG))
00276     {
00277         __asm__ __volatile__ (
00278             "in __tmp_reg__,__SREG__" "\n\t"
00279             "cli" "\n\t"
00280             "wdr" "\n\t"
00281             "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
00282             "sts %[WDTREG],%[WDVALUE]" "\n\t"
00283             "out __SREG__,__tmp_reg__" "\n\t"
00284             : /* no outputs */
00285             : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),
00286             [SIGNATURE] "r" ((uint8_t)0xD8),
00287             [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
00288             [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
00289                 | _BV(WDE) | (value & 0x07) ))
00290             : "r0"
00291             );
00292     }
00293     else
00294     {
00295         __asm__ __volatile__ (
00296             "in __tmp_reg__,__SREG__" "\n\t"
00297             "cli" "\n\t"
00298             "wdr" "\n\t"
00299             "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
00300             "out %[WDTREG],%[WDVALUE]" "\n\t"
00301             "out __SREG__,__tmp_reg__" "\n\t"
00302             : /* no outputs */
00303             : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),
00304             [SIGNATURE] "r" ((uint8_t)0xD8),
00305             [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
00306             [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00)
00307                 | _BV(WDE) | (value & 0x07) ))
00308             : "r0"
00309             );
00310     }
00311 }
00312 
00313 static __inline__
00314 __attribute__ ((__always_inline__))
00315 void wdt_disable (void)
00316 {
00317     if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG))
00318     {
00319         uint8_t temp_wd;
00320         __asm__ __volatile__ (
00321                 "in __tmp_reg__,__SREG__" "\n\t"
00322                 "cli" "\n\t"
00323                 "wdr" "\n\t"
00324                 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
00325                 "lds %[TEMP_WD],%[WDTREG]" "\n\t"
00326                 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
00327                 "sts %[WDTREG],%[TEMP_WD]" "\n\t"
00328                 "out __SREG__,__tmp_reg__" "\n\t"
00329                 : /*no output */
00330                 : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)),
00331                 [SIGNATURE] "r" ((uint8_t)0xD8),
00332                 [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
00333                 [TEMP_WD] "d" (temp_wd),
00334                 [WDVALUE] "n" (1 << WDE)
00335                 : "r0"
00336                 );
00337     }
00338     else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P(_WD_CONTROL_REG))
00339     {
00340         uint8_t temp_wd;
00341         __asm__ __volatile__ (
00342                 "in __tmp_reg__,__SREG__" "\n\t"
00343                 "cli" "\n\t"
00344                 "wdr" "\n\t"
00345                 "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t"
00346                 "in %[TEMP_WD],%[WDTREG]" "\n\t"
00347                 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
00348                 "out %[WDTREG],%[TEMP_WD]" "\n\t"
00349                 "out __SREG__,__tmp_reg__" "\n\t"
00350                 : /*no output */
00351                 : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)),
00352                 [SIGNATURE] "r" ((uint8_t)0xD8),
00353                 [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
00354                 [TEMP_WD] "d" (temp_wd),
00355                 [WDVALUE] "n" (1 << WDE)
00356                 : "r0"
00357                 );
00358     }
00359     else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG))
00360     {
00361         uint8_t temp_wd;
00362         __asm__ __volatile__ (
00363                 "in __tmp_reg__,__SREG__" "\n\t"
00364                 "cli" "\n\t"
00365                 "wdr" "\n\t"
00366                 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
00367                 "lds %[TEMP_WD],%[WDTREG]" "\n\t"
00368                 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
00369                 "sts %[WDTREG],%[TEMP_WD]" "\n\t"
00370                 "out __SREG__,__tmp_reg__" "\n\t"
00371                 : /*no output */
00372                 : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),
00373                 [SIGNATURE] "r" ((uint8_t)0xD8),
00374                 [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
00375                 [TEMP_WD] "d" (temp_wd),
00376                 [WDVALUE] "n" (1 << WDE)
00377                 : "r0"
00378                 );
00379     }
00380     else
00381     {
00382         uint8_t temp_wd;
00383         __asm__ __volatile__ (
00384                 "in __tmp_reg__,__SREG__" "\n\t"
00385                 "cli" "\n\t"
00386                 "wdr" "\n\t"
00387                 "out %[CCPADDRESS],%[SIGNATURE]" "\n\t"
00388                 "in %[TEMP_WD],%[WDTREG]" "\n\t"
00389                 "cbr %[TEMP_WD],%[WDVALUE]" "\n\t"
00390                 "out %[WDTREG],%[TEMP_WD]" "\n\t"
00391                 "out __SREG__,__tmp_reg__" "\n\t"
00392                 : /*no output */
00393                 : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)),
00394                 [SIGNATURE] "r" ((uint8_t)0xD8),
00395                 [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
00396                 [TEMP_WD] "d" (temp_wd),
00397                 [WDVALUE] "n" (1 << WDE)
00398                 : "r0"
00399                 );
00400     }
00401 }
00402 
00403 #else
00404 
00405 static __inline__
00406 __attribute__ ((__always_inline__))
00407 void wdt_enable (const uint8_t value)
00408 {
00409     if (_SFR_IO_REG_P (_WD_CONTROL_REG))
00410     {
00411         __asm__ __volatile__ (
00412                 "in __tmp_reg__,__SREG__" "\n\t"
00413                 "cli" "\n\t"
00414                 "wdr" "\n\t"
00415                 "out %0, %1" "\n\t"
00416                 "out __SREG__,__tmp_reg__" "\n\t"
00417                 "out %0, %2" "\n \t"
00418                 : /* no outputs */
00419                 : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
00420                 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
00421                 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
00422                         _BV(WDE) | (value & 0x07)) )
00423                 : "r0"
00424         );
00425     }
00426     else
00427     {
00428         __asm__ __volatile__ (
00429                 "in __tmp_reg__,__SREG__" "\n\t"
00430                 "cli" "\n\t"
00431                 "wdr" "\n\t"
00432                 "sts %0, %1" "\n\t"
00433                 "out __SREG__,__tmp_reg__" "\n\t"
00434                 "sts %0, %2" "\n \t"
00435                 : /* no outputs */
00436                 : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
00437                 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
00438                 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
00439                         _BV(WDE) | (value & 0x07)) )
00440                 : "r0"
00441         );
00442     }
00443 }
00444 
00445 static __inline__
00446 __attribute__ ((__always_inline__))
00447 void wdt_disable (void)
00448 {
00449     if (_SFR_IO_REG_P (_WD_CONTROL_REG))
00450     {
00451         uint8_t register temp_reg;
00452         __asm__ __volatile__ (
00453                 "in __tmp_reg__,__SREG__"    "\n\t"
00454                 "cli"                        "\n\t"
00455                 "wdr"                        "\n\t"
00456                 "in  %[TEMPREG],%[WDTREG]"   "\n\t"
00457                 "ori %[TEMPREG],%[WDCE_WDE]" "\n\t"
00458                 "out %[WDTREG],%[TEMPREG]"   "\n\t"
00459                 "out %[WDTREG],__zero_reg__" "\n\t"
00460                 "out __SREG__,__tmp_reg__"   "\n\t"
00461                 : [TEMPREG] "=d" (temp_reg)
00462                 : [WDTREG]  "I"  (_SFR_IO_ADDR(_WD_CONTROL_REG)),
00463                 [WDCE_WDE]  "n"  ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE)))
00464                 : "r0"
00465         );
00466     }
00467     else
00468     {
00469         uint8_t register temp_reg;
00470         __asm__ __volatile__ (
00471                 "in __tmp_reg__,__SREG__"    "\n\t"
00472                 "cli"                        "\n\t"
00473                 "wdr"                        "\n\t"
00474                 "lds %[TEMPREG],%[WDTREG]"   "\n\t"
00475                 "ori %[TEMPREG],%[WDCE_WDE]" "\n\t"
00476                 "sts %[WDTREG],%[TEMPREG]"   "\n\t"
00477                 "sts %[WDTREG],__zero_reg__" "\n\t"
00478                 "out __SREG__,__tmp_reg__"   "\n\t"
00479                 : [TEMPREG] "=d" (temp_reg)
00480                 : [WDTREG]  "n"  (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
00481                 [WDCE_WDE]  "n"  ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE)))
00482                 : "r0"
00483         );
00484     }
00485 }
00486 
00487 #endif
00488 
00489 
00490 /**
00491    \ingroup avr_watchdog
00492    Symbolic constants for the watchdog timeout.  Since the watchdog
00493    timer is based on a free-running RC oscillator, the times are
00494    approximate only and apply to a supply voltage of 5 V.  At lower
00495    supply voltages, the times will increase.  For older devices, the
00496    times will be as large as three times when operating at Vcc = 3 V,
00497    while the newer devices (e. g. ATmega128, ATmega8) only experience
00498    a negligible change.
00499 
00500    Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
00501    500 ms, 1 s, 2 s.  (Some devices also allow for 4 s and 8 s.)
00502    Symbolic constants are formed by the prefix
00503    \c WDTO_, followed by the time.
00504 
00505    Example that would select a watchdog timer expiry of approximately
00506    500 ms:
00507    \code
00508    wdt_enable(WDTO_500MS);
00509    \endcode
00510 */
00511 #define WDTO_15MS   0
00512 
00513 /** \ingroup avr_watchdog
00514     See \c WDTO_15MS */
00515 #define WDTO_30MS   1
00516 
00517 /** \ingroup avr_watchdog
00518     See \c WDTO_15MS */
00519 #define WDTO_60MS   2
00520 
00521 /** \ingroup avr_watchdog
00522     See \c WDTO_15MS */
00523 #define WDTO_120MS  3
00524 
00525 /** \ingroup avr_watchdog
00526     See \c WDTO_15MS */
00527 #define WDTO_250MS  4
00528 
00529 /** \ingroup avr_watchdog
00530     See \c WDTO_15MS */
00531 #define WDTO_500MS  5
00532 
00533 /** \ingroup avr_watchdog
00534     See \c WDTO_15MS */
00535 #define WDTO_1S     6
00536 
00537 /** \ingroup avr_watchdog
00538     See \c WDTO_15MS */
00539 #define WDTO_2S     7
00540 
00541 #if defined(__DOXYGEN__) || defined(WDP3)
00542 
00543 /** \ingroup avr_watchdog
00544     See \c WDTO_15MS
00545     Note: This is only available on the 
00546     ATtiny2313, 
00547     ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
00548     ATtiny25, ATtiny45, ATtiny85, 
00549     ATtiny261, ATtiny461, ATtiny861, 
00550     ATmega48, ATmega88, ATmega168,
00551     ATmega48P, ATmega88P, ATmega168P, ATmega328P,
00552     ATmega164P, ATmega324P, ATmega644P, ATmega644,
00553     ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
00554     ATmega8HVA, ATmega16HVA, ATmega32HVB,
00555     ATmega406, ATmega1284P,
00556     AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
00557     AT90PWM81, AT90PWM161,
00558     AT90USB82, AT90USB162,
00559     AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
00560     ATtiny48, ATtiny88.
00561     */
00562 #define WDTO_4S     8
00563 
00564 /** \ingroup avr_watchdog
00565     See \c WDTO_15MS
00566     Note: This is only available on the 
00567     ATtiny2313, 
00568     ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
00569     ATtiny25, ATtiny45, ATtiny85, 
00570     ATtiny261, ATtiny461, ATtiny861, 
00571     ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168,
00572     ATmega48P, ATmega88P, ATmega168P, ATmega328P,
00573     ATmega164P, ATmega324P, ATmega644P, ATmega644,
00574     ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
00575     ATmega8HVA, ATmega16HVA, ATmega32HVB,
00576     ATmega406, ATmega1284P,
00577     ATmega2564RFR2, ATmega256RFR2, ATmega1284RFR2, ATmega128RFR2, ATmega644RFR2, ATmega64RFR2
00578     AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
00579     AT90PWM81, AT90PWM161,
00580     AT90USB82, AT90USB162,
00581     AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
00582     ATtiny48, ATtiny88,
00583     ATxmega16a4u, ATxmega32a4u,
00584     ATxmega16c4, ATxmega32c4,
00585     ATxmega128c3, ATxmega192c3, ATxmega256c3.
00586     */
00587 #define WDTO_8S     9
00588 
00589 #endif  /* defined(__DOXYGEN__) || defined(WDP3) */
00590    
00591 
00592 #endif /* _AVR_WDT_H_ */
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